Power management for system-on-chip
A system-on-chip comprises processing circuitry to process input data to generate output data, and power management circuitry to control power management policy for at least a portion of the system-on-chip. The power management circuitry controls the power management policy depending on metadata indicative of a property of the input data to be processed by the processing circuitry.
1 . A system-on-chip comprising:
processing circuitry configured to process input data to generate output data; and
power management circuitry configured to control power management policy for at least a portion of the system-on-chip, in which the power management policy comprises a maximum power mitigation policy, wherein the power management circuitry is configured to restrict throughput of the processing circuitry in response to determining that a number of monitored power-intensive events over an evaluation period exceeds a pre-defined threshold; in which:
the input data comprises input data for a machine learning workload to be performed by the processing circuitry, wherein the machine learning workload implements a convolutional neural network;
the power management circuitry is configured to control a mode of the maximum power mitigation policy depending on metadata indicative of a property of the input data to be processed by the processing circuitry in the machine learning workload, in which the mode of the maximum power mitigation policy comprises settings for at least one of:
detection or weighting of the power-intensive events; and
the pre-defined threshold;
and
the power management circuitry is configured to determine, based on the metadata associated with the input data to be processed by the processing circuitry, a load/store overhead estimate indicative of an estimated overhead associated with loading the input data or storing the output data, and control the mode of the maximum power mitigation policy based on the load/store overhead estimate, in which the load/store overhead estimate is indicative of an estimated overhead incurred by at least one of:
a load/store unit configured to control issuing of load/store requests to a memory system;
an interconnect configured to control routing of memory access requests across the system-on-chip;
access to on-chip memory storage circuitry;
access to off-chip memory storage circuitry; and
loss of processing efficiency at the processing circuitry due to load/store delays.
2 . The system-on-chip according to claim 1 , in which the power management circuitry is configured to select a power management policy setting for a forthcoming period based on the metadata indicative of the property of the input data to be processed by the processing circuitry in the forthcoming period.
3 . The system-on-chip according to claim 1 , in which the metadata is indicative of at least one of:
sparsity of the input data;
a compression property associated with a compressed version of the input data;
a range or distribution of numeric values within the input data; and
a property of inter-value differences between successive data values of the input data.
4 . The system-on-chip according to claim 1 , in which the metadata is indicative of a property of kernel weights provided as the input data for a convolutional neural network.
5 . The system-on-chip according to claim 1 , in which the metadata is indicative of a property of input neural network data or at least one input feature map provided as the input data for a convolutional neural network.
6 . The system-on-chip according to claim 1 , in which the power management circuitry is configured to make separate power management policy decisions for processing of respective portions of the input data, based on portion metadata associated with the respective portions.
7 . The system-on-chip according to claim 1 , in which the power management circuitry is configured to determine, based on the metadata associated with the input data to be processed by the processing circuitry, a compute overhead estimate indicative of an estimated overhead associated with computation of the output data based on the input data, and control the power management policy based on the compute overhead.
8 . The system-on-chip according to claim 3 , comprising predicate generating circuitry configured to generate, based on the metadata, predicates for predicated instructions to be supplied to the processing circuitry for processing the input data, the predicates indicating one or more inactive elements of the input data for which processing operations are to be masked.
9 . The system-on-chip according to claim 1 , in which the setting for the maximum power mitigation policy comprises
a throughput limit indicative of a maximum throughput allowed when the power management circuitry determines that throughput of the processing circuitry should be restricted.
10 . The system-on-chip according to claim 1 , in which:
the power management circuitry is configured to control the maximum power mitigation policy to favor more strongly restricting the throughput when the metadata indicates a first condition of the input data than when the metadata indicates a second condition of the input data;
in the first condition, the metadata indicates less sparse input data than in the second condition;
in the first condition, the metadata indicates input data supporting a smaller level of compression than in the second condition;
in the first condition, the metadata indicates that the input data has a wider range of numeric values than in the second condition;
in the second condition, the metadata indicates that a distribution of numeric values within the input data is clustered more heavily around zero than in the first condition; or
in the first condition, the metadata indicates that an average of inter-value differences between successive data values of the input data is greater than in the second condition.
11 . The system-on-chip according to claim 1 , wherein
the power management circuitry is configured to control the power management policy by causing the processing circuitry to perform one or more dummy operations, based on the metadata indicative of the property of the input data, to limit a rate of change in power requirement.
12 . The system-on-chip according to claim 1 , in which the power management policy controlled depending on the metadata comprises dynamic voltage scaling.
13 . The system-on-chip according to claim 1 , wherein
the processing circuitry comprises a plurality of execution engines, and the power management policy controlled depending on the metadata indicative of the property of the input data comprises control of how many of the plurality of execution engines are active.
14 . The system-on-chip according to claim 1 , in which the processing circuitry comprises at least one of:
a central processing unit (CPU);
a graphics processing unit (GPU);
a hardware accelerator; and
a neural processing unit (NPU).