IP Library Granted Patent US 8,412,479
Granted Patent B2
US 8,412,479 · App. 12/826,039 · Granted Apr 2, 2013

Memory power estimation by means of calibrated weights and activity counters

Inventors: Howard S. David (Portland, OR); Eugene Gorbatov (Hillsboro, OR); Ulf R. Hanebutte (Gig Harbor, WA); Minh Le (North Plains, OR); Rahul Khanna (Portland, OR)
Assignee: Intel Corporation
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Quick Facts
Patent No.
US 8,412,479
App. No.
12/826,039
Granted
Apr 2, 2013
Kind
B2
Abstract

Memory power estimation by means of calibrated weights and activity counters are generally presented. In this regard, in one embodiment, a memory power is introduced to read a value from a memory activity counter, to determine a memory power estimation based at least in part on the value and a calibration, and to store the memory power estimation to a register. Other embodiments are also described and claimed.

Claims (21)

1. A storage medium comprising content which, when executed by an accessing machine, causes the accessing machine to:

read a value from a memory activity counter;

determine a memory power estimation based at least in part on the value and a calibration;

store the memory power estimation to a register; and

determine the calibration based on an execution of a memory access test pattern comprising receiving a current measurement from a voltage regulator across various memory loadings to determine specific characteristics of the voltage regulator.

2. The storage medium of claim 1 , wherein the content to read a value from a memory activity counter comprises content to read a counter containing a value chosen from the group consisting of: active memory reads, active memory writes, enable activates, clock enable percentage, and self-refresh percentage.

3. The storage medium of claim 1 , further comprising content which, when executed by an accessing machine, causes the accessing machine to read a plurality of values from a plurality of memory activity counters and determine the memory power estimation based at least in part on the plurality of values and a set of calibrations.

4. A system comprising:

a processor including a memory controller and a memory activity counter;

a dynamic random access memory (DRAM) coupled to the processor; and

a memory power agent, the memory power agent to read a value from the memory activity counter, the memory power agent to determine a memory power estimation based at least in part on the value and a calibration, and the memory power agent to store the memory power estimation to a register, the memory power agent to determine the calibration based on an execution of a memory access test pattern, the memory power agent to receive a plurality of current measurements from a voltage regulator across various memory loadings to determine specific characteristics of the voltage regulator.

5. The system of claim 4 , wherein the memory power agent to read a value from a memory activity counter comprises the memory power agent to read a counter containing a value chosen from the group consisting of: active memory reads, active memory writes, enable activates, clock enable percentage, and self-refresh percentage.

6. The system of claim 4 , further comprising the memory power agent to read a plurality of values from a plurality of memory activity counters and determine the memory power estimation based at least in part on the plurality of values and a set of calibrations.

7. A method for estimating a memory power consumption in a computing system comprising:

determining a calibration based on an execution of a memory access test pattern;

reading a value from a memory activity counter; computing a memory power estimation based at least in part on the value and a calibration; and

storing the memory power estimation to a register;

wherein determining the calibration based on the execution of a memory access test pattern comprises receiving a current measurement from a voltage regulator, wherein receiving a current measurement from a voltage regulator comprises receiving a plurality of current measurements from a voltage regulator across various memory loadings to determine specific characteristics of the voltage regulator.

8. The method of claim 7 , wherein determining the calibration based on the execution of a memory access test pattern comprises executing the memory access test pattern during a system boot.

9. The method of claim 7 , wherein reading a value from a memory activity counter comprises reading a counter containing a value chosen from the group consisting of: active memory reads, active memory writes, enable activates, clock enable percentage, and self-refresh percentage.

10. The method of claim 7 , further comprising reading a plurality of values from a plurality of memory activity counters and computing the memory power estimation based at least in part on the plurality of values and a set of calibrations.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2013
From: DAVID, HOWARD S.; GORBATOV, EUGENE; HANEBUTTE, ULF R.; LE, MINH; KHANNA, RAHUL
To: INTEL CORPORATION
Reel/Frame 029899/0381 →
Continuity (1)
Related Publication 20110320150A1 · Dec 29, 2011