Semiconductor device including a normal mode, a debug mode, and a key

1. A semiconductor device comprising:

a first system including a first operation circuit; and

a second system configured to control a debug operation in the first system,

wherein the semiconductor device includes a normal mode and a debug mode,

in the debug mode of the semiconductor device, where the semiconductor device is in the debug mode, a first key received from an outside corresponds to a second key stored in the second system, and a debug target designated in a debug command is not an address range in which an access authority is requested, the second system transmits the debug command to the first operation circuit, and

where the semiconductor device is in the debug mode, the first key corresponds to the second key, and the debug target designated in the debug command is an address range in which an access authority is requested, the second system transmits the debug command to the first operation circuit based on a third key received from an outside.

2. The device according to claim 1 , wherein the second system includes a second operation circuit, and

in the debug mode of the semiconductor device, in a case where the semiconductor is in the debug mode, and the first key corresponds to the second key, the second operation circuit brings the second system into a state in which the debug command is receivable from an outside.

3. The device according to claim 2 , wherein the second system further includes a communication port configured to perform a communication with an outside via a network, and

the second system receives the debug command from an outside via the communication port.

4. The device according to claim 1 , wherein the second system further includes a table, and

when in a case where the semiconductor is in the debug mode, the first key corresponds to the second key, the debug target designated in the debug command is an address range in which an access authority is requested, in a case where and the third key corresponds to a fourth key corresponding to the address range designated in the debug command within the table, the second system transmits the debug command to the first operation circuit.

5. The device according to claim 1 , wherein at power-on, in a case where the second system does not receive the first key, the second system selects the normal mode, and in a case where the second system receives the first key, the second system selects the debug mode.

6. The device according to claim 1 , wherein the second system further includes a switch, and

at power-on, in a case where the switch is in an OFF state, the second system selects the normal mode, and in a case where the switch is in an ON state, the second system selects the debug mode.

7. The device according to claim 6 , wherein in a case where the switch is switched from the OFF state to the ON state, the second system selects the debug mode, and in a case where the switch is switched from the ON state to the OFF state, the second system selects the normal mode.

8. A system comprising:

a semiconductor device including:

a first system including a first operation circuit;

a second system configured to control a debug operation in the first system; and

a computer configured to communicate with the second system via a network,

wherein the semiconductor device includes a normal mode and a debug mode,

in the debug mode of the semiconductor device, where the semiconductor device is in the debug mode, a first key received from an outside corresponds to a second key stored in the second system, and a debug target designated in a debug command is not an address range in which an access authority is requested, the second system transmits the debug command to the first operation circuit, and

where the semiconductor device is in the debug mode, the first key corresponds to the second key, and the debug target designated in the debug command is an address range in which an access authority is requested, the second system transmits the debug command to the first operation circuit based on a third key received from an outside.