Memory system for storing meta data and operating method thereof
The present technology relates to a memory system and a method of operating the same. The memory system includes a semiconductor memory device including a plurality of meta blocks and a plurality of normal blocks, and a controller for controlling the semiconductor memory device to generate meta data and store the generated meta data in a target meta block selected from among the plurality of meta blocks. The controller converts an address so that the address of the meta data corresponds to a selected sub block of the selected target meta block.
1 . A memory system comprising:
a semiconductor memory device configured to include a plurality of memory blocks and a peripheral circuit, wherein the plurality of memory blocks are connected to the peripheral circuit through word lines and bit lines, and the plurality of memory blocks comprise a plurality of meta blocks; and
a controller configured to control the semiconductor memory device to store meta data in in a selected meta block among the plurality of meta blocks,
wherein the selected meta block includes:
a first sub-block used for storing the meta data,
a second sub-block used for storing information and data on an overall operation currently being performed during a sudden power off of the memory system, and
a third sub-block used for replacing a bad block among the plurality of memory blocks, and
wherein the controller is further configured to:
allocate remaining meta blocks other than the selected meta block to store data other than the meta data, and
allocate each of the first, second, and third sub-blocks for a respective function, and
wherein the first sub-block, the second sub-block, the third sub-block are capable of being erased independently.
2 . The memory system of claim 1 , wherein the controller generates the meta data, allocates the selected meta block to the meta data, and converts an address of the meta data to an address of the first sub-block among a plurality of sub-blocks included in the selected memory block.
3 . The memory system of claim 2 , wherein the meta data include mapping information between logical addresses and physical addresses of data stored in the semiconductor memory device.
4 . The memory system of claim 1 , wherein the remaining meta blocks are used as at least one of a single-level cell (SLC) block, a replacement block, or an overprovisioning block.
5 . A controller for controlling a semiconductor memory device including a plurality of memory blocks and a peripheral circuit, wherein the plurality of memory blocks are connected to the peripheral circuit through word lines and bit lines, and the plurality of memory blocks comprise a plurality of meta blocks the controller comprising:
a host interface configured to receive a command from an external host; and
a processor configured to generate meta data related to the command and to control the semiconductor memory device to store the meta data in a portion of selected meta block among the plurality of meta blocks,
wherein the selected meta block includes:
a first sub-block used for storing the meta data,
a second sub-block used for storing information and data on an overall operation currently being performed during a sudden power off of the memory system, and
a third sub-block used for replacing a bad block among the plurality of memory blocks,
wherein the processor is further configured to:
allocate remaining meta blocks other than the selected meta block to store data other than the meta data, and
allocate each of the first, second, and third sub-blocks for a respective function, and
wherein the first sub-block, the second sub-block, the third sub-block are capable of being erased independently.
6 . The memory system of claim 5 , wherein the processing unit comprises:
a flash translation layer configured to generate a command queue for controlling the semiconductor memory device in response to a command received from the external host;
a meta data generator configured to generate the meta data for a command operation corresponding to the command; and
an address converter configured to convert an address of the meta data generated by the meta data generator into an address of the first sub-blocks.
7 . The memory system of claim 6 , wherein the meta data includes information on command data corresponding to the command received from the external host, information on the command operation, information on normal blocks of the semiconductor memory device on which the command operation is performed, and information on map data corresponding to the command operation.
8 . A method of operating a controller of a semiconductor memory device including a plurality of memory blocks and a peripheral circuit, wherein the plurality of memory blocks are connected to the peripheral circuit through word lines and bit lines, and the plurality of memory blocks comprise a plurality of meta blocks, the method comprising:
generating meta data in response to a command received from a host;
allocating one memory block among the plurality of meta blocks to store the meta data;
converting an address of the meta data into an address of a first sub-block among a plurality of sub-blocks included in the one memory block;
transmitting the meta data to the semiconductor memory device and storing the meta data in the first sub-block; and
allocating remaining meta blocks other than the one memory block to store data other than the meta data,
wherein the one memory block includes:
the first sub-block used for storing the meta data,
a second sub-block used for storing information and data on an overall operation currently being performed during a sudden power off of the memory system, and
a third sub-block used for replacing a bad block among the plurality of memory blocks,
wherein the first sub-block, the second sub-block, the third sub-block are capable of being erased independently, and
wherein each of the first, second, and third sub-blocks is allocated for a respective function.