Storage system and method for improving read performance using multiple copies of a logical-to-physical address table
A storage system and method for improving read performance using multiple copies of a logical-to-physical address table are provided. In one embodiment, a method for parallelism is provided that is performed in a storage system comprising a plurality of memory areas accessible in parallel, wherein each memory area stores a copy of a logical-to-physical address table. The method comprises reading portions of the logical-to-physical address tables in parallel from the plurality of memory areas, wherein the portions comprise translations for logical addresses associated with a plurality of memory commands; translating the logical addresses associated with the plurality of memory commands into physical addresses using the read portions; and performing the plurality of memory commands. Other embodiments are provided.
1. A method for parallelism in a storage system, the method comprising:
performing the following in a storage system comprising a plurality of memory areas accessible in parallel, wherein each memory area stores an identical copy of a logical-to-physical address table:
reading portions of the identical copies of the logical-to-physical address table in parallel from the plurality of memory areas, wherein the portions comprise translations for logical addresses associated with a plurality of memory commands;
translating the logical addresses associated with the plurality of memory commands into physical addresses using the read portions; and
performing the plurality of memory commands.
2. The method of claim 1 , wherein all of the portions of the logical-to-physical address tables are read before any of the memory commands are performed.
3. The method of claim 1 , wherein at least some of the plurality of memory commands are performed in parallel.
4. The method of claim 1 , wherein the plurality of memory commands comprise at least one of a read command and a write command.
5. The method of claim 1 , wherein at least one of the plurality of memory commands comprises a write command,
wherein performing the write command results in a change to one of the logical-to-physical address tables, and
wherein the method further comprises marking the logical-to-physical address tables that have not been changed as obsolete.
6. The method of claim 5 further comprising updating the logical-to-physical address tables marked as obsolete per the change made to the one of the logical-to-physical address tables.
7. The method of claim 5 ,
wherein each copy of the logical-to-physical address table is identified by a respective sequence number,
wherein the markings as to which logical-to-physical address tables are obsolete are erased during a power loss, and
wherein the method further comprises, after the power loss, identifying which logical-to-physical address tables are obsolete based on which logical-to-physical address tables have a sequence number lower than a highest sequence number among all the logical-to-physical address tables.
8. The method of claim 1 , wherein the storage system comprises a three-dimensional memory.
9. The method of claim 1 , wherein the plurality of memory areas comprise a plurality of memory dies.
10. The method of claim 1 , wherein the plurality of memory areas comprise a plurality of planes in a memory die.
11. A method for parallelism in a storage system, the method comprising:
performing the following in a storage system comprising a plurality of memory areas accessible in parallel, wherein each memory area stores an identical copy of a logical-to-physical address table:
identifying a first memory area associated with a first memory operation;
identifying a second memory area from which to read the logical-to-physical address table to translate a logical address associated with a second memory operation; and
performing the first memory operation in the first memory area in parallel with reading the logical-to-physical address table from the second memory area.
12. The method of claim 11 , wherein the memory operation comprises one of a read command and a write command.
13. The method of claim 11 , wherein the plurality of memory areas comprise a plurality of memory dies.
14. The method of claim 11 , wherein the plurality of memory areas comprise a plurality of planes in a memory die.
15. The method of claim 11 , wherein the storage system comprises a three-dimensional memory.
16. A storage system comprising: a memory comprising
a plurality of memory areas accessible in parallel, each memory area storing an identical copy of a table; and
at least one of the following:
means for reading the identical copies of the table from the plurality of memory areas in parallel prior to performing a memory operation in one of the plurality of memory areas so that reading the identical copies of the table does not prevent the memory operation from being performed in the one of the plurality of memory areas; and
means for determining which memory area to read the identical copy of the table from so that the identical copy of the table is read in parallel with a memory operation being performed in another one of the memory areas.
17. The storage system of claim 16 , wherein the table comprises a logical-to-physical address table.
18. The storage system of claim 16 , wherein the memory comprises a three-dimensional memory.
19. The storage system of claim 16 , wherein the storage system is embedded in a host.
20. The storage system of claim 16 , wherein the storage system is removably connectable from a host.