MIM eFuse memory devices and memory array

1. A memory device, comprising:

a transistor; and

a resistor electrically connected to the transistor, the transistor and the resistor forming a first one-time programmable (OTP) memory cell,

wherein the resistor includes a metal-based layer with a resistivity configured to irreversibly transition from a first resistance state to a second resistance state, and

wherein the metal-based layer has a first surface and a second surface, the first surface in direct contact with a via structure that is disposed between adjacent ones of a plurality of metallization layers, the second surface in direct contact with an interconnect structure that is disposed in one of the plurality of metallization layers, the first surface and the second surface being opposite to each other.

2. The memory device of claim 1 , further comprising a first interconnect structure coupled to a source/drain (S/D) structure of the transistor, wherein the metal-based layer is disposed with respect to the first interconnect structure.

3. The memory device of claim 2 , wherein the metal-based layer is interposed between the first interconnect structure and the S/D structure.

4. The memory device of claim 2 , wherein the metal-based layer is disposed above the first interconnect structure.

5. The memory device of claim 2 , wherein the plurality of metallization layers are disposed over the first interconnect structure, wherein the metal-based layer is disposed within a first one of the metallization layers.

6. The memory device of claim 5 , wherein the first metallization layer includes an interconnect structure located farther than the metal-based layer to the transistor, and the metal-based layer is located farther than a via structure to the transistor.

7. The memory device of claim 5 , wherein a via structure is located farther than the metal-based layer from the transistor, and the metal-based layer is located farther than an interconnect structure of the first metallization layer from the transistor.

8. The memory device of claim 1 , further comprising a via structure coupled to the transistor, wherein the via structure has a first portion connected to a first interconnect structure and a second portion connected to a second interconnect structure, and wherein the resistor is disposed between the first and second portions of the via structure.

9. The memory device of claim 1 , wherein the metal-based layer includes a material selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), alloy of Ti and TiN, alloy of Ta and TaN, and combinations thereof.

10. A memory array, comprising:

a substrate; and

a memory array disposed over the substrate and comprising a plurality of one-time programmable (OTP) memory cells, each of the OTP memory cells comprising a transistor and a resistor electrically connected to each other,

wherein the resistor of each of the OTP memory cells is formed of a metal-based material configured to present a low resistance state prior to programming the corresponding memory cell and a high resistance state in response to programming the corresponding memory cell, and

wherein the resistor has a first surface and a second surface, the first surface in direct contact with a via structure that is disposed between adjacent ones of a plurality of metallization layers, the second surface in direct contact with an interconnect structure that is disposed in one of the plurality of metallization layers, the first surface and the second surface being opposite to each other.

11. The memory device of claim 10 , wherein the metal-based material of each of the OTP memory cells is selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), alloy of Ti and TiN, alloy of Ta and TaN, and combinations thereof.

12. The memory device of claim 11 , wherein the resistor of each of the OTP memory cell is formed over a source/drain structure of the transistor of the respective OTP memory cell.

13. A memory device, comprising:

a transistor; and

a resistor electrically connected to the transistor, the transistor and the resistor forming a one-time programmable (OTP) memory cell,

wherein the resistor includes a metal-based layer including a material allowing a resistivity of the resistor to irreversibly transition from a first resistance state to a second resistance state,

wherein the metal-based layer has a first surface and a second surface, the first surface in direct contact with a via structure that is disposed between adjacent ones of a plurality of metallization layers, the second surface in direct contact an interconnect structure that is disposed in one of the plurality of metallization layers, the first surface and the second surface being opposite to each other.

14. The memory device of claim 13 , wherein the material is selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), alloy of Ti and TiN, alloy of Ta and TaN, and combinations thereof.

15. The memory device of claim 13 , further comprising:

a first interconnect structure in direct contact with a source/drain (S/D) structure of the transistor;

a first via structure having two opposite surfaces in direct contact with the first interconnect structure and the first surface of the metal-based layer, respectively; and

a second interconnect structure in direct contact with the second surface of the metal-based layer.

16. The memory device of claim 15 , wherein the first interconnect structure and the second interconnect structure are disposed in the adjacent metallization layers, respectively.

17. The memory device of claim 13 , further comprising:

a first interconnect structure indirectly coupled to a source/drain (S/D) structure of the transistor;

a first via structure having two opposite surfaces in direct contact with the first interconnect structure and the first surface of the metal-based layer, respectively; and

a second interconnect structure in direct contact with the second surface of the metal-based layer.

18. The memory device of claim 17 , wherein the first interconnect structure and the second interconnect structure are disposed in the adjacent metallization layers, respectively.

19. The memory device of claim 18 , wherein one or more of the metallization layers are formed between the adjacent metallization layers and the S/D structure of the transistor.