Double metal layout for memory cells of a non-volatile memory

1. An integrated circuit, comprising:

a first fuse fabricated on a first conductive layer of the integrated circuit;

a second fuse fabricated on a second conductive layer of the integrated circuit, wherein the first and second conductive layers are different layers of the integrated circuit; and

a transistor fabricated on a front-end-of-the-line (FEOL) structure of the integrated circuit;

wherein a first memory cell of a non-volatile memory is provided by a first memory circuit comprising the first fuse and the transistor, and a second memory cell of the non-volatile memory is provided by a second memory circuit comprising the second fuse and the transistor.

2. The integrated circuit of claim 1 , further comprising:

a third fuse fabricated on the first conductive layer of the integrated circuit; and

a fourth fuse fabricated on the second conductive layer of the integrated circuit;

wherein a third memory cell of the non-volatile memory is provided by a third memory circuit comprising the third fuse and the transistor, and a fourth memory cell of the non-volatile memory is provided by a fourth memory circuit comprising the fourth fuse and the transistor.

3. The integrated circuit of claim 1 , further comprising:

a third fuse fabricated on the first conductive layer of the integrated circuit;

a fourth fuse fabricated on the second conductive layer of the integrated circuit; and

a second transistor fabricated on the FEOL structure of the integrated circuit;

wherein a third memory cell of the non-volatile memory is provided by a third memory circuit comprising the third fuse and the second transistor, and a fourth memory cell of the non-volatile memory is provided by a fourth memory circuit comprising the fourth fuse and the second transistor.

4. The integrated circuit of claim 1 , wherein the non-volatile memory is a read-only memory (ROM).

5. The integrated circuit of claim 1 , wherein at least a portion of the first fuse is fabricated on an area of the first conductive layer that is above at least a portion of the second fuse fabricated on the second conductive layer.

6. The integrated circuit of claim 1 , wherein the first fuse and the second fuse are coupled to a current-carrying node of the transistor.

7. The integrated circuit of claim 6 , wherein a first bit line of the non-volatile memory is coupled to the first fuse, a second bit line of the non-volatile memory is coupled to the second fuse, and a word line of the non-volatile memory is coupled to a gate node of the transistor.

8. The integrated circuit of claim 1 , wherein the first and second fuses each comprise a fuse link and a plurality of conductive spacers, wherein the plurality of conductive spacers electrically isolate the fuse link from one or more other semiconductor components of the integrated circuit.

9. A method of manufacturing an integrated circuit, comprising:

fabricating a transistor on a front-end-of-the-line (FEOL) structure of the integrated circuit;

fabricating a first fuse on a first conductive layer of a back-end-of-the-line (BEOL) structure of the integrated circuit;

fabricating a second fuse on a second conductive layer of the BEOL structure of the integrated circuit, wherein the first and second conductive layers are different layers of the integrated circuit;

electrically coupling the first fuse to a current-carrying node of the transistor to provide a first memory cell for a non-volatile memory; and

electrically coupling the second fuse to the current-carrying node of the transistor to provide a second memory cell for the non-volatile memory.

10. The method of claim 9 , further comprising:

fabricating a third fuse on the first conductive layer of the integrated circuit;

fabricating a fourth fuse on the second conductive layer of the integrated circuit;

electrically coupling the third fuse to the transistor to provide a third memory cell for the non-volatile memory; and

electrically coupling the fourth fuse to the transistor to provide a fourth memory cell for the non-volatile memory.

11. The method of claim 9 , further comprising:

fabricating a second transistor on the FEOL structure of the integrated circuit;

fabricating a third fuse on the first conductive layer of the integrated circuit;

fabricating a fourth fuse on the second conductive layer of the integrated circuit;

electrically coupling the third fuse to the second transistor to provide a third memory cell for the non-volatile memory; and

electrically coupling the fourth fuse to the second transistor to provide a fourth memory cell for the non-volatile memory.

12. The method of claim 9 , wherein the non-volatile memory is a read-only memory (ROM).

13. The method of claim 9 , wherein at least a portion of the first fuse is fabricated on an area of the first conductive layer that is above at least a portion of the second fuse fabricated on the second conductive layer.

14. The method of claim 9 , wherein the first fuse and the second fuse are coupled to a current-carrying node of the transistor.

15. The method of claim 14 , wherein a first bit line of the non-volatile memory is coupled to the first fuse, a second bit line of the non-volatile memory is coupled to the second fuse, and a word line of the non-volatile memory is coupled to a gate node of the transistor.

16. The method of claim 9 , wherein the first and second fuses each comprise a fuse link and a plurality of conductive spacers, wherein the plurality of conductive spacers electrically isolate the fuse link from one or more other semiconductor components of the integrated circuit.

17. A non-volatile memory, comprising:

a plurality of memory cells that include a first memory cell and a second memory cell;

the first memory cell including a first eFuse fabricated on a first conductive layer of the non-volatile memory;

the second memory cell including a second eFuse fabricated on a second conductive layer of the integrated circuit, wherein the first and second conductive layers are different layers of the integrated circuit.

18. The non-volatile memory of claim 17 , wherein the first and second eFuses are coupled to a transistor fabricated on a front-end-of-the-line (FEOL) structure of the non-volatile memory.

19. The non-volatile memory of claim 18 , wherein:

the plurality of memory cells include a third memory cell and a fourth memory cell;

the third memory cell including a third eFuse coupled to the transistor, wherein the third eFuse is fabricated on the first conductive layer;

the fourth memory cell including a fourth eFuse coupled to the transistor, wherein the fourth eFuse is fabricated on the second conductive layer.

20. The non-volatile memory of claim 18 , wherein:

the plurality of memory cells include a third memory cell and a fourth memory cell;

the third memory cell including a third eFuse coupled to a second transistor, wherein the third eFuse is fabricated on the first conductive layer and the second transistor is fabricated on the FEOL structure;

the fourth memory cell including a fourth eFuse coupled to the second transistor, wherein the fourth eFuse is fabricated on the second conductive layer.