One-time-programmable memory devices and methods for forming the same
A memory device is disclosed. The memory device includes a memory cell comprising: a transistor; and a plurality of pairs of resistors coupled to the transistor in series, each of the pairs of resistors including a first resistor and a second resistor. The transistor is formed along a major surface of a substrate. At least a first one of the pairs of resistors are formed in a first one of a plurality of metallization layers disposed above the transistor. At least a second one of the pairs of resistors are formed in a second one of the plurality of metallization layers, the second metallization layer being disposed above the first metallization layer.
1 . A memory device, comprising:
a memory cell comprising:
a transistor; and
one or more pairs of resistors coupled to the transistor in series, each of the one or more pairs of resistors including a first resistor and a second resistor;
wherein the transistor is formed along a major surface of a substrate, and the one or more pairs of resistors are respectively formed in one or more of a plurality of metallization layers disposed above the transistor;
wherein the first resistor is formed of a first dielectric material laterally between a via structure and a first conductive line; and
wherein the second resistor is formed of a second dielectric material laterally between the via structure and a second conductive line.
2 . The memory device of claim 1 , wherein the memory cell is configured as a one-time-programmable memory cell, in which one of the first resistor or the second resistor is configured to permanently switch from a first resistance state to a second resistance state.
3 . The memory device of claim 1 , wherein a first pair of the one or more pairs of resistors are formed in a first layer of the plurality of metallization layers, and a second pair of the one or more pairs of resistors are formed in a second layer of the plurality of metallization layers, and wherein the first layer is vertically spaced from the second layer.
4 . The memory device of claim 1 , wherein the first conductive line and the second conductive line are formed in an identical one of the plurality of metallization layers.
5 . The memory device of claim 1 , wherein the via structure has a lower portion laterally interposed between the first conductive line and the second conductive line.
6 . The memory device of claim 1 , wherein the first dielectric material and the second dielectric material each include transition metal oxide.
7 . The memory device of claim 1 , wherein the via structure, the first conductive line, and the second conductive line each include copper.
8 . The memory device of claim 1 , wherein the transistor is part of a front-end-of-line (FEOL) network, and the one or more pairs of resistors are part of a back-end-of-line (BEOL) network.
9 . A memory device, comprising:
a memory cell comprising:
a transistor; and
a plurality of pairs of resistors coupled to the transistor in series, each of the plurality of pairs of resistors including a first resistor and a second resistor;
wherein the transistor is formed along a major surface of a substrate;
wherein at least a first pair of the plurality of pairs of resistors are formed in a first layer of a plurality of metallization layers disposed above the transistor;
wherein, for each respective pair of the plurality of pairs of resistors:
the first resistor of the respective pair is formed of a first dielectric material laterally between a via structure and a first conductive line; and
the second resistor of the respective pair is formed of a second dielectric material laterally between the via structure and a second conductive line.
10 . The memory device of claim 9 , wherein the memory cell is configured as a one-time-programmable memory cell, in which one of the first resistor or the second resistor is configured to permanently switch from a first resistance state to a second resistance state.
11 . The memory device of claim 9 , wherein the first conductive line and the second conductive line are formed in an identical one of the plurality of metallization layers.
12 . The memory device of claim 9 , wherein the via structure has a lower portion laterally interposed between the first conductive line and the second conductive line.
13 . The memory device of claim 9 , wherein the first dielectric material and the second dielectric material each include transition metal oxide.
14 . The memory device of claim 9 , wherein the via structure, the first conductive line, and the second conductive line each include copper.
15 . The memory device of claim 9 , wherein the via structure has an upper portion that vertically extends away from the first conductive line and the second conductive line.
16 . A memory device, comprising:
a memory cell comprising:
a transistor; and
a first resistor and a second resistor each coupled to the transistor in series;
wherein the transistor is formed along a major surface of a substrate;
wherein the first resistor and the second resistor are both formed in one metallization layer of a plurality of metallization layers disposed above the transistor; and
wherein the first resistor and the second resistor are disposed symmetrically to each other with respect to a via structure.
17 . The memory device of claim 16 ,
wherein the first resistor is formed based on a first dielectric material laterally between the via structure and a first conductive line, and the second resistor is formed based on a second dielectric material laterally between the via structure and a second conductive line; and
wherein the first conductive line and the second conductive line are disposed at the one metallization layer.
18 . The memory device of claim 16 , wherein the memory cell is configured as a one-time-programmable memory cell, in which one of the first resistor or the second resistor is configured to permanently switch from a first resistance state to a second resistance state.