Silicon carbide MOSFET device and manufacturing method thereof
View Patent ↗Disclosed a silicon carbide MOSFET device and manufacturing method thereof. The method includes: forming a patterned first barrier layer on an upper surface of the substrate; forming a base region of a second doping type extending from the upper surface to an inside of the substrate through oblique implantation in a first ion implantation process by using a first barrier layer as a mask; forming a source region of the first doping type in the substrate; forming a contact region of the second doping type in the substrate; and forming a gate structure, an implantation angle of the first ion implantation process is adjusted so that the base region extends below a part of the first barrier layer. The method of the present disclosure not only reduces one photoetching process and saves cost, but also realizes a short channel and reduces an on-resistance of the device.
1. A manufacturing method of a silicon carbide MOSFET device, comprising:
providing a substrate of a first doping type;
forming a patterned first barrier layer on an upper surface of the substrate;
forming a base region extending from the upper surface to an inside of the substrate through oblique implantation in a first ion implantation process by using a first barrier layer as a mask, the base region is of a second doping type;
forming a source region of the first doping type in the substrate;
forming a contact region of the second doping type in the substrate; and
forming a gate structure,
wherein, an implantation angle of the first ion implantation process is adjusted so that the base region extends below a part of the first barrier layer, and the implantation angle of the first ion implantation process is an angle between an implanting direction of the first ion implantation process and the upper surface of the substrate; and
wherein forming the source region comprises:
forming a second barrier layer on the upper surface of the substrate; and
forming the source region extending from the upper surface to the inside of the substrate through self-aligned implantation in a second ion implantation process by using the first barrier layer and the second barrier layer as a mask,
wherein, the second barrier layer is located between the first barrier layers and is separated from the first barrier layer.
2. The manufacturing method according to claim I., wherein by rotating the implantation direction of the first ion implantation process, both sides of the base region extend below the part of the first barrier layer.
3. The manufacturing method according to claim 1 , wherein by controlling the implantation angle of the first ion implantation process, a width of the base region extending below the first barrier layer is controlled.
4. The manufacturing method according to claim 1 , wherein the smaller the implantation angle of the first ion implantation process, the greater a width of the base region extending below the first barrier layer.
5. The manufacturing method according to claim 1 , wherein by controlling an implantation energy of the first ion implantation process, a width of the base region extending below the first barrier layer is controlled.
6. The manufacturing method according to claim 1 , wherein the greater an implantation energy of the first ion implantation process, the greater a width of the base region extending below the first barrier layer.
7. The manufacturing method according to claim 1 , wherein the implantation angle of the first ion implantation process is 45°.
8. The manufacturing method according to claim 1 wherein a material of the first barrier layer is different from a material of the second barrier layer.
9. The manufacturing method according to claim 1 , wherein further comprises: removing the second barrier layer after forming the source region.
10. A manufacturing method of a silicon carbide MOSFET device, comprising:
providing a substrate of a first doping type;
forming a patterned first barrier layer on an upper surface of the substrate;
forming a base region extending from the upper surface to an inside of the substrate through oblique implantation in a first ion implantation process by using a first barrier layer as a mask the base region is of a second doping type;
forming a source region of the first doping type in the substrate
forming a contact region of the second doping type in the substrate; and
forming a gate structure,
wherein, an implantation angle of the first ion implantation process is adjusted so that the base region extends below a part of the first barrier layer, and the implantation angle of the first ion implantation process is an angle between an implanting direction of the first ion implantation process and the upper surface of the substrate;
wherein forming the contact region comprises:
forming a shielding layer on an upper surface and sidewalls of the first barrier layer and the upper surface of the substrate; and
forming the contact region extending from the upper surface to the inside of the substrate through self-aligned implantation in a third ion implantation process by using the first barrier layer and the shielding layer as a mask,
wherein, the third ion implantation process implants dopants into the substrate through the shielding layer located on the upper surface of the substrate to form the contact region, a stacking part of the first barrier layer and the shielding layer and the shielding layer on a sidewall of the first barrier layer resists the implantation of the third ion implantation process.
11. The manufacturing method according to claim 10 , wherein a thickness of the shielding layer is not more than half of a thickness of the first barrier layer.
12. The manufacturing method according to claim 10 , wherein a thickness of the shielding layer ranges from 800 to 1200 angstroms.
13. The manufacturing method according to claim 10 , wherein a material of the first barrier layer is the same as a material of the shielding layer.
14. The manufacturing method according to claim 10 , wherein further comprises:
removing the shielding layer after forming the contact region.
15. The manufacturing method according to claim 1 , wherein a step of forming the contact region comprises:
forming the contact region extending from the upper surface to the inside of the substrate through self-aligned implantation in a second ion implantation process by using the first barrier layer as a mask,
wherein a width of the contact region is smaller than a width of the base region.
16. The manufacturing method according to claim 1 , wherein a step of forming the source region comprises:
at least etching part of a thickness of the first barrier layer in a lateral direction;
forming a third barrier layer between the etched first barrier layers; and
forming the source region extending from the upper surface to the inside of the substrate through self-aligned implantation in a third ion implantation process by using the etched first barrier layer and the third barrier layer as a mask,
wherein, a thickness of the etched first barrier layer is smaller than a width of the base region extending below the first barrier layer.
17. The manufacturing method according to claim 16 , wherein a material of the first barrier layer is different from a. material of the third barrier layer.
18. The manufacturing method according to claim 16 , wherein the thickness of the etched first barrier layer ranges from 800 to 1200 angstroms.
19. The manufacturing method according to claim 16 , wherein the first barrier layer is etched by an isotropic etching process.
20. The manufacturing method according to claim 16 , wherein removing the etched first battier layer and the third barrier layer after forming the source region.
21. The manufacturing method according to claim 1 , wherein a step of forming the gate structure comprises:
forming a gate dielectric layer on the upper surface of the substrate; and
forming a gate conductor on a part of an upper surface of the gate dielectric layer;
wherein, the gate conductor covers at least part of the source region and the base region.
22. The manufacturing method according to claim 21 , wherein further comprises:
depositing an interlayer dielectric layer on the gate dielectric layer and the gate conductor, forming an opening exposing an upper surface of the contact region and part of an upper surface of the source region by etching the interlayer dielectric layer and the gate dielectric layer,
forming a source metal in the opening, and
forming a drain metal on a back surface of the substrate.
23. The manufacturing method according to claim 1 , wherein the one of N-type and P-type, and the second doping type is the other of N-type and P-type.
24. A silicon carbide MOSFET device formed according to the manufacturing method of claim 1 , and
wherein the gate structure is disposed on the upper surface of the substrate, and
wherein, a junction depth of the contact region and a junction depth of the source region are smaller than a junction depth of the base region, a width of the contact region is smaller than a width of the base region, and the source region is located on and in contact with both sides of the contact region.
25. A silicon carbide MOSFET device formed according to the manufacturing method of claim 22 ,
wherein the gate structure is disposed on the upper surface of the substrate, and covers at least part of the source region and the base region;
wherein source metal covers the source region and the contact region through the opening, and
wherein, a junction depth of the contact region and a junction depth of the source region are smaller than a junction depth of the base region, a width of the contact region is smaller than a width of the base region, and the source region is located on and in contact with both sides of the contact region.