Integrated circuit device and method of manufacturing the same

1. An integrated circuit device comprising:

a fin-type active region extending in a first horizontal direction on a substrate;

a channel region on the fin-type active region;

a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction;

an insulating spacer covering a sidewall of the gate line;

a source/drain region connected to the channel region on the fin-type active region and comprising a first portion facing the sidewall of the gate line with the insulating spacer therebetween;

an air gap between the insulating spacer and the first portion of the source/drain region;

an insulating liner comprising a portion in contact with the source/drain region and a portion defining a size of the air gap; and

a device isolation layer between the substrate and the gate line and covering a sidewall of the fin-type active region,

wherein the air gap comprises a portion between a top surface of the device isolation layer and the source/drain region.

2. The integrated circuit device of claim 1 , wherein the insulating liner comprises a portion defining a height of the air gap in a vertical direction and a portion defining a width of the air gap in the second horizontal direction.

3. The integrated circuit device of claim 1 ,

wherein a top surface of the device isolation layer is exposed to the air gap.

4. The integrated circuit device of claim 1 , wherein the insulating spacer comprises a first sidewall portion exposed to the air gap,

wherein the first portion of the source/drain region is exposed to the air gap and faces the first sidewall portion of the insulating spacer with the air gap therebetween.

5. The integrated circuit device of claim 1 , wherein the channel region comprises a plurality of nanosheets facing a fin top surface of the fin-type active region at a position vertically apart from the fin top surface of the fin-type active region and having different vertical distances from the fin top surface, wherein a sidewall of each of the plurality of nanosheets is in contact with the insulating spacer.

6. The integrated circuit device of claim 1 , wherein two sidewalls of a portion of the source/drain region in the second horizontal direction, the portion being adjacent to the channel region, are exposed to the air gap.

7. The integrated circuit device of claim 1 , wherein a size and shape of a cross-section of a portion of the air gap in the second horizontal direction, the portion being adjacent to the source/drain region, corresponds to a size and shape of a cross-section of the source/drain region in the second horizontal direction.

8. The integrated circuit device of claim 1 , wherein a size of a cross-section of a portion of the air gap in the second horizontal direction, the portion being adjacent to the source/drain region, is less than a size of a cross-section of the source/drain region in the second horizontal direction.

9. The integrated circuit device of claim 1 ,

wherein the insulating spacer comprises a lower portion region in contact with the device isolation layer and the source/drain region, and

the insulating liner comprises a portion vertically overlapping the lower portion region.

10. The integrated circuit device of claim 1 , further comprising:

a residual insulating layer between the device isolation layer and the insulating liner in a vertical direction and exposed to the air gap,

wherein the residual insulating layer comprises a material different from that of the insulating spacer.

11. An integrated circuit device comprising:

a first fin-type active region extending in a first horizontal direction in a first device region on a substrate;

a first channel region on the first fin-type active region;

a first gate line surrounding the first channel region on the first fin-type active region and extending in a second horizontal direction crossing the first horizontal direction;

a first source/drain region connected to the first channel region on the first fin-type active region and comprising a first portion facing a sidewall of the first gate line;

a first air gap between the first gate line and the first portion of the first source/drain region;

a second fin-type active region extending in the first horizontal direction in a second device region on the substrate;

a second channel region on the second fin-type active region;

a second gate line surrounding the second channel region on the second fin-type active region and extending in the second horizontal direction;

a second source/drain region connected to the second channel region on the second fin-type active region and comprising a second portion facing a sidewall of the second gate line; and

a second air gap between the second gate line and the second portion of the second source/drain region and having a size different from that of the first air gap.

12. The integrated circuit device of claim 11 , further comprising:

a first insulating spacer between the first gate line and the first air gap in the first device region and having a portion exposed to the first air gap; and

a second insulating spacer between the second gate line and the second air gap in the second device region and having a portion exposed to the second air gap.

13. The integrated circuit device of claim 11 , further comprising:

a first insulating spacer between the first gate line and the first air gap in the first device region and having a portion exposed to the first air gap;

a first insulating liner comprising a portion in contact with the first source/drain region in the first device region, a portion in contact with the first insulating spacer, and a portion defining a size of the first air gap;

a second insulating spacer between the second gate line and the second air gap in the second device region and having a portion exposed to the second air gap; and

a second insulating liner comprising a portion in contact with the second source/drain region in the second device region, a portion in contact with the second insulating spacer, and a portion defining a size of the second air gap,

wherein a material of the first insulating spacer differs from that of the first insulating liner, and

a material of the second insulating spacer differs from that of the second insulating liner.

14. The integrated circuit device of claim 11 , wherein the first source/drain region comprises a Si layer doped with an n-type dopant, and

the second source/drain region comprises a SiGe layer doped with a p-type dopant.

15. The integrated circuit device of claim 11 , wherein the first channel region comprises a plurality of first nanosheets vertically apart from a first fin top surface of the first fin-type active region and surrounded by the first gate line, and

the second channel region comprises a plurality of second nanosheets vertically apart from a second fin top surface of the second fin-type active region and surrounded by the second gate line.

16. The integrated circuit device of claim 11 , further comprising:

a plurality of first nanosheets vertically apart from a first fin top surface of the first fin-type active region and surrounded by the first gate line, the plurality of first nanosheets forming a portion of the first channel region;

a first gate dielectric layer covering the first gate line between each two of the plurality of first nanosheets;

a plurality of inner insulating spacers between the first source/drain region and the first gate dielectric layer;

a plurality of second nanosheets vertically apart from a second fin top surface of the second fin-type active region and surrounded by the second gate line, the plurality of second nanosheets forming a portion of the second channel region; and

a second gate dielectric layer covering the second gate line between each two of the plurality of second nanosheets,

wherein the first source/drain region is apart from the first gate dielectric layer with the plurality of inner insulating spacers therebetween, and

wherein the second source/drain region is in contact with the second gate dielectric layer.

17. An integrated circuit device comprising:

a fin-type active region extending in a first horizontal direction on a substrate and having a fin top surface;

a nanosheet stack comprising a plurality of nanosheets facing the fin top surface at a position vertically apart from the fin top surface and having different vertical distances from the fin top surface;

a gate line surrounding the plurality of nanosheets on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction;

an insulating spacer covering a sidewall of the gate line;

a source/drain region connected to the plurality of nanosheets on the fin-type active region and comprising a first portion facing the sidewall of the gate line with the insulating spacer therebetween;

an air gap between the insulating spacer and the first portion of the source/drain region; and

an insulating liner comprising a portion in contact with the source/drain region, a portion in contact with the insulating spacer, and a portion defining a size of the air gap, the insulating liner comprising a material different from that of the insulating spacer.

18. The integrated circuit device of claim 17 , wherein the insulating spacer comprises a SiOCN layer, a SiON layer, or a combination thereof, and the insulating liner comprises a SiN layer.

19. The integrated circuit device of claim 17 , wherein a size of a cross-section of a portion of the air gap in the second horizontal direction, the portion being adjacent to the source/drain region, is equal to or less than a size of a cross-section of the source/drain region in the second horizontal direction.