Integrated circuit with backside trench for metal gate definition

1. A method, comprising:

forming a first channel region of a first transistor over a substrate;

forming a second channel region of a second transistor over the substrate;

depositing a gate metal on the first channel region and on the second channel region; and

electrically isolating a first gate electrode of the first transistor from a second gate electrode of the second transistor by forming a first trench from a backside of the substrate through the gate metal.

2. The method of claim 1 , further comprising filling the first trench with a dielectric material.

3. The method of claim 2 , further comprising depositing a liner layer on a sidewall of the trench in the substrate prior to filling the trench with the dielectric material.

4. The method of claim 2 , further comprising:

forming a third channel region of a third transistor;

depositing the gate metal over the third channel region; and

electrically isolation the second gate electrode of the second transistor from a third gate electrode of the third transistor by forming a second trench from the back side of the substrate through the gate metal, wherein the second trench is formed after the first trench.

5. The method claim 4 , wherein forming the second trench includes removing a first part and a second part, wherein the second part has a width smaller than the first part along a direction along a first channel of the first channel region.

6. A method, comprising:

attaching a carrier wafer to a front side of an integrated circuit in a substrate;

electrically isolating a gate electrode of a first transistor from a gate electrode of a second transistor by forming a first trench from a backside of the integrated circuit through a gate metal while the carrier wafer is attached to the integrated circuit; and

filling the first trench with a first dielectric material.

7. The method of claim 6 , further comprising reducing a thickness of the substrate while the carrier wafer is attached and before etching the first trench.

8. The method of claim 6 , wherein etching the first trench includes etching the first trench through a trench isolation region of the substrate.

9. The method of claim 8 , further comprising:

etching second and third trenches through a semiconductor material of the substrate from the backside of the wafer while the carrier wafer is attached and before etching the first trench; and

filling the second and third trenches with a second dielectric material.

10. The method of claim 9 , further comprising:

etching the first trench in the substrate between the second and third trenches; and

depositing a dielectric liner on sidewalls of the first trench in contact with the second dielectric material prior to filling the first trench with the first dielectric material.

11. The method of claim 6 , wherein the first dielectric material includes SiCN or silicon oxynitride.

12. A method, comprising:

forming a substrate including semiconductor material and a trench isolation region;

forming a first nanosheet transistor over the substrate and having a first gate electrode, a first plurality of stacked channels, and a first dielectric fin structure below the first plurality of stacked channels;

forming a second nanosheet transistor over the substrate and having a second gate electrode, a second plurality of stacked channels, and a second dielectric fin structure below the second plurality of stacked channels;

removing the semiconductor material of the substrate below the first plurality of stacked channels and the second plurality of stacked channels;

depositing a first dielectric material in placed of the removed semiconductor material to form a first dielectric fin structure below the first plurality of stacked channels and to form a second dielectric fin structure below the second plurality of stacked channels;

forming a trench through the trench isolation region between the first and second dielectric fin structures and through a gate metal connecting the first gate electrode to the second gate electrode; and

forming a gate isolation structure between the first nanosheet transistor and the second nanosheet transistor by depositing a second dielectric material in the trench.

13. The method of claim 12 , wherein a bottommost surface of the gate isolation structure is substantially coplanar with a bottommost surface of the first dielectric fin structure.

14. The integrated circuit of claim 12 , wherein the gate isolation structure has an upper portion and a lower portion, wherein the upper portion is wider than the lower portion along a direction along the first gate electrode.

15. The integrated circuit of claim 12 , wherein the gate isolation structure has an upper portion and a lower portion, wherein the upper portion of the gate isolation structure includes the second dielectric material, wherein the lower portion of the gate isolation structure includes a third dielectric material different material from the lower portion.

16. The method of claim 12 , further comprising forming a liner layer on a sidewall of the trench below the first gate electrode and the second gate electrode prior to depositing the second dielectric material.

17. The method of claim 16 , wherein the liner layer is present in the trench below the first and second gate electrodes but is not present above the substrate.

18. The method of claim 12 , wherein the gate isolation structure has an upper portion and a lower portion, wherein the upper portion includes a first part in contact with the lower portion and a second part in contact with the lower portion, and the first part includes a different material from the second part.

19. The method of claim 18 , wherein the first part includes a same material as the lower portion.

20. The method of claim 12 , further comprising forming a bonding layer between the gate isolation structure and the substrate.