Semiconductor backside isolation feature for merged epitaxy
A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors. Each field effect transistor includes source/drain regions located on opposite sides of the field effect transistors. A shallow trench isolation region located between adjacent field effect transistors electrically separates the plurality of field effect transistors from one another. The shallow trench isolation region has a tapered profile. A backside isolation region is embedded within the shallow trench isolation region and cuts through the source/drain regions. The backside isolation region has a reverse tapered profile.
1 . A semiconductor structure, comprising:
a front-end-of-line level including a plurality of field effect transistors, each field effect transistor including source/drain regions located on opposite sides of the field effect transistors;
a shallow trench isolation region located between adjacent field effect transistors for electrically separating the plurality of field effect transistors from one another, the shallow trench isolation region having a tapered profile; and
a backside isolation region embedded within the shallow trench isolation region and cutting through the source/drain regions, the backside isolation region having a reverse tapered profile.
2 . The semiconductor structure of claim 1 , wherein the backside isolation region having the reverse tapered profile comprises:
a top portion of the backside isolation region embedded within the source/drain regions having a first critical dimension; and
a bottom portion of the backside isolation region embedded within the shallow trench isolation region having a second critical dimension, wherein the second critical dimension is larger than the first critical dimension.
3 . The semiconductor structure of claim 1 , further comprising:
a shallow trench isolation liner surrounding a bottom an opposite sidewalls of the shallow trench isolation region.
4 . The semiconductor structure of claim 3 , wherein the shallow trench isolation liner is, at least in part, in contact with the bottom portion of the backside isolation region.
5 . The semiconductor structure of claim 1 , further comprising:
an interlevel dielectric layer deposited above the field effect transistors; and
a backside interlevel dielectric dispose below the field effect transistors.
6 . The semiconductor structure of claim 5 , further comprising:
a metal contact within the interlevel dielectric layer, the metal contact electrically connecting a first side of at least one source/drain region to a back-end-of-line level.
7 . The semiconductor structure of claim 6 , further comprising:
a placeholder layer within the backside interlevel dielectric, the placeholder layer being located on a second side of the at least one source/drain region opposing the first side of the at least one source/drain region.
8 . The semiconductor structure of claim 5 , further comprising:
a backside metal contact within the backside interlevel dielectric layer, the backside metal contact electrically connecting a second side of at least another source/drain region to a backside power rail, wherein a first side of the at least another source/drain region is in contact with the interlevel dielectric layer.
9 . The semiconductor structure of claim 6 , further comprising:
a carrier wafer located above the back-end-of-line level.
10 . The semiconductor structure of claim 8 , further comprising:
a backside power delivery network deposited above the backside power rail.
11 . The semiconductor structure of claim 1 , wherein each of the field effect transistors further comprises:
a gate structure located above and surrounding a plurality of channel layers, wherein the gate structure of a field effect transistor is electrically isolated from the gate structure of an adjacent field effect transistor by a gate cut isolation region.
12 . The semiconductor structure of claim 11 , wherein the backside isolation region is in contact with the gate cut isolation region in a gate region of the semiconductor structure.