Access transistor including a metal oxide barrier layer and methods for forming the same
A transistor may be provided by forming, in a forward order or in a reverse order, a gate electrode, a semiconducting metal oxide liner, a gate dielectric, and an active layer over a substrate, and by forming a source electrode and a drain electrode on end portions of the active layer. The semiconducting metal oxide liner comprises a thin semiconducting metal oxide material that functions as a hydrogen barrier material.
1 . A transistor comprising:
a gate electrode located over a substrate;
a hydrogen barrier structure comprising a planar semiconducting metal oxide liner contacting a surface of the gate electrode, wherein the planar semiconducting metal oxide liner contains hydrogen;
a gate dielectric contacting a surface of the planar semiconducting metal oxide liner and spaced from the gate electrode by the planar semiconducting metal oxide liner;
an active layer contacting the gate dielectric; and
a source electrode and a drain electrode located on end portions of the active layer,
wherein sidewalls of the planar semiconducting metal oxide liner are vertically coincident with sidewalls of the active layer, which are vertical and connect a top surface of the active layer to a bottom surface of the active layer.
2 . The transistor of claim 1 , wherein the planar semiconducting metal oxide liner comprises a material selected from indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, and doped cadmium oxide.
3 . The transistor of claim 1 , wherein:
the planar semiconducting metal oxide liner has a thickness in a range from 0.1 nm to 3 nm; and
the active layer has a thickness that is at least three times the thickness of the planar semiconducting metal oxide liner.
4 . The transistor of claim 1 , wherein the planar semiconducting metal oxide liner comprises a horizontal surface that contacts an entirety of a horizontal surface of the gate dielectric.
5 . The transistor of claim 4 , wherein the sidewalls of the active layer are vertically coincident with sidewalls of the gate dielectric in a plan view.
6 . The transistor of claim 4 , wherein:
the gate electrode is embedded in a dielectric material portion;
the planar semiconducting metal oxide liner contacts a first surface of the dielectric material portion; and
the gate dielectric contacts a second surface of the dielectric material portion.
7 . The transistor of claim 1 , further comprising a conformal semiconducting metal oxide liner laterally surrounding, and contacting a bottom surface of, the gate electrode, wherein a top surface of vertically-extending portions of the conformal semiconducting metal oxide liner contacts a bottom surface of the planar semiconducting metal oxide liner.
8 . The transistor of claim 1 , further comprising a tubular metal oxide liner laterally surrounding the gate electrode, wherein an inner periphery of a bottom surface of the tubular metal oxide liner coincides with a periphery of a bottom surface of the gate electrode, and a top surface of the tubular metal oxide liner contacts a bottom surface of the planar semiconducting metal oxide liner.
9 . The transistor of claim 1 , further comprising a word line underlying, and electrically connected to, the gate electrode and having a lateral extent along a lengthwise direction that is greater than a lateral extent of the active layer along a lengthwise direction of the active layer in a plan view.
10 . The transistor of claim 1 , wherein the sidewalls of the hydrogen-containing planar semiconducting metal oxide liner are vertically coincident with sidewalls of the gate dielectric.
11 . A transistor comprising:
an active layer located over a substrate;
a gate dielectric contacting a surface of the active layer;
a source electrode and a drain electrode located on end portions of the active layer;
a hydrogen barrier structure comprising a conformal semiconducting metal oxide liner that is vertically spaced from, and not in direct contact with, the gate dielectric, wherein the semiconducting metal oxide liner contains hydrogen; and
a gate electrode embedded in the conformal semiconducting metal oxide liner and spaced from the gate dielectric by the conformal semiconducting metal oxide liner, wherein sidewalls of the planar semiconducting metal oxide liner are vertically coincident with sidewalls of the active layer, which are vertical and connect a top surface of the active layer to a bottom surface of the active layer.
12 . The transistor of claim 11 , wherein the conformal semiconducting metal oxide liner comprises:
a planar semiconducting portion contacting a bottom surface of the gate electrode; and
a tubular portion adjoined to a periphery of the planar semiconducting portion and contacting sidewalls of the gate electrode.
13 . The transistor of claim 11 , further comprising a planar semiconducting metal oxide liner extending parallel to an interface between the active layer and the gate dielectric and contacting a planar semiconducting surface of the gate electrode that is not in contact with the conformal semiconducting metal oxide liner.
14 . The transistor of claim 11 , wherein the conformal semiconducting metal oxide liner comprises a material selected from indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, and doped cadmium oxide.
15 . The transistor of claim 11 , further comprising:
a dielectric layer laterally surrounding the active layer, the source electrode, and the drain electrode;
a source contact via structure contacting the source electrode; and
a drain contact via structure contacting the drain electrode.
16 . A transistor comprising:
an active layer located over a substrate;
a gate dielectric contacting a surface of the active layer;
a source electrode and a drain electrode located on end portions of the active layer;
a hydrogen barrier structure comprising a planar semiconducting metal oxide liner contacting the gate dielectric, wherein the semiconducting metal oxide liner contains hydrogen;
a conformal semiconducting metal oxide liner contacting the planar semiconducting metal oxide liner; and
a gate electrode embedded in the conformal semiconducting metal oxide liner and spaced from the gate dielectric by the conformal semiconducting metal oxide liner, wherein sidewalls of the planar semiconducting metal oxide liner are vertically coincident with sidewalls of the active layer, which are vertical and connect a top surface of the active layer to a bottom surface of the active layer.
17 . The transistor of claim 16 , wherein the conformal semiconducting metal oxide liner comprises a tubular portion adjoined to a periphery of the planar semiconducting portion and contacting sidewalls of the gate electrode.
18 . The transistor of claim 17 , wherein the conformal semiconducting metal oxide liner comprises a planar semiconducting portion contacting a bottom surface of the gate electrode.
19 . The transistor of claim 16 , wherein the conformal semiconducting metal oxide liner comprises a material selected from indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, and doped cadmium oxide.
20 . The transistor of claim 16 , further comprising:
a dielectric layer laterally surrounding the active layer, the source electrode, and the drain electrode;
a source contact via structure contacting the source electrode; and
a drain contact via structure contacting the drain electrode.