Shielded socket and carrier for high-volume test of semiconductor devices

1. A test apparatus comprising:

an interface board affixed in a slot of a tester rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT);

a carrier comprising an array of DUTs and a plurality of membrane pockets operable to hold the array of DUTs, wherein the carrier is operable to be inserted into the slot of the tester rack, and wherein each DUT in the array of DUTs aligns with a respective socket of the plurality of sockets on the interface board; and

a plurality of socket covers, wherein each socket cover of the plurality of socket covers is operable to actuate a top portion of each DUT of the array of DUTs in the carrier to cause each DUT to push through a respective membrane pocket to contact the respective socket.

2. The test apparatus of claim 1 , wherein each respective socket cover of the plurality of socket covers is actuated by applying downward force on the top portion of each respective DUT.

3. The test apparatus of claim 1 , wherein each respective socket of the plurality of sockets, the carrier and an associated respective socket cover of the plurality of socket covers together form an RF shield around an associated DUT.

4. The test apparatus of claim 1 , wherein the plurality of socket covers are associated with a parallel cover assembly system configured to align and place each of the plurality of socket covers over a respective DUT from the array of DUTs.

5. The test apparatus of claim 1 , further comprising:

a plunger operable to push down on each socket cover of the plurality of socket covers to bring a respective DUT into closer contact with a respective socket.

6. The test apparatus of claim 1 , wherein each respective socket of the plurality of sockets, the carrier and an associated respective socket cover of the plurality of socket covers together form an RF shield around an associated DUT, wherein the associated DUT comprises an RF device.

7. The test apparatus of claim 1 , wherein each DUT in the array of DUTs is held in the respective membrane pocket of the carrier, wherein a ball-grid array on the bottom of each DUT is operable to push through the respective membrane pocket to contact the respective socket when a respective socket cover is actuated.

8. The test apparatus of claim 1 , wherein each socket cover of the plurality of socket covers is aligned with a respective socket using pogo pins.

9. A method of testing DUTs comprising:

affixing an interface board in a slot of a tester rack, wherein the interface board comprises a plurality of sockets, and wherein each socket of the plurality of sockets is operable to receive a device under test (DUT);

inserting an array of DUTs disposed on a carrier into the slot of the tester rack, wherein the carrier comprises a plurality of membrane pockets operable to hold the array of DUTs, wherein each respective DUT in the array of DUTs aligns with a respective socket on the interface board; and

actuating a socket cover of a plurality of socket covers onto each DUT in the array of DUTs to push the respective DUT to push through a respective membrane pocket to make contact with the respective socket of the plurality of sockets.

10. The method of claim 9 , wherein each respective socket of the plurality of sockets, the carrier and an associated respective socket cover of the plurality of socket covers together form an electrical shield around an associated DUT.

11. The method of claim 9 , wherein each respective socket of the plurality of sockets, the carrier and an associated respective socket cover of the plurality of socket covers together form an RF shield around an associated DUT, wherein the associated DUT comprises an RF device.

12. The method of claim 9 , wherein the plurality of socket covers are placed onto the array of DUTs using a parallel cover assembly system configured to simultaneously align and place each of the plurality of socket covers on a respective DUT of the array of DUTs.

13. The method of claim 9 , wherein each DUT in the array of DUTs is held in the respective membrane pocket of the carrier, wherein a ball-grid array on the bottom of each DUT is operable to push through the respective membrane pocket to make contact with the respective socket of the plurality of sockets when a respective socket cover of the plurality of socket covers is actuated.

14. A tester system comprising:

a tester chamber comprising a plurality of slots, wherein each slot of the plurality of slots comprises:

an interface board affixed in a respective slot of the tester chamber, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT);

a carrier comprising an array of DUTs and a plurality of membrane pockets operable to hold the array of DUTs, wherein the carrier is operable to slide into the respective slot, and wherein each DUT in the array of DUTs aligns with a respective socket on the interface board; and

a plunger comprising a plurality of integrated socket covers, wherein the plunger is configured to apply downward force on each of the plurality of integrated socket covers onto a top portion of a respective DUT of the array of DUTs in the carrier to cause the respective DUT to push through a respective membrane pocket to contact the respective socket.

15. The tester system of claim 14 , wherein each respective socket of the plurality of sockets, the carrier and an associated respective integrated socket cover of the plurality of integrated socket covers together form an electrical shield around an associated DUT.

16. The tester system of claim 14 , wherein each respective socket of the plurality of sockets, the carrier and an associated respective integrated socket cover of the plurality of integrated socket covers together form an RF shield around an associated DUT, wherein the associated DUT comprises an RF device.

17. The tester system of claim 14 , wherein the array of DUTs comprises RF devices.

18. The tester system of claim 14 , wherein each DUT in the array of DUTs is held in the respective membrane pocket of the carrier, wherein a ball-grid array on the bottom of each DUT is operable to push through the respective membrane pocket to make contact with the respective socket when a respective integrated socket cover is actuated.

19. The tester system of claim 14 , wherein each integrated socket cover of the plurality of integrated socket covers is aligned with a respective socket using pogo pins.

20. The tester system of claim 14 , further comprising an elevator operable to move the carrier vertically to the respective slot.