Vertical stacked nanosheet CMOS transistors with different work function metals
A method for forming a semiconductor device includes forming a structure having at least a first nanosheet stack for a first device, a second nanosheet stack for a second device and disposed over the first nanosheet stack, a disposable gate structure, and a gate spacer. The disposable gate structure and sacrificial layers of the first and second nanosheet stacks are removed thereby forming a plurality of cavities. A conformal gate dielectric layer is formed in the plurality cavities and surrounding at least portions of the first and second nanosheet stacks. A first conformal work function layer is formed in contact with the gate dielectric layer. Portions of the first conformal work function layer are removed without using a mask from at least the second nanosheet stack. A second conformal work function layer is formed on exposed portions of the gate dielectric layer.
1. A semiconductor device comprising at least:
a first nanosheet stack for a first device of a first channel type, wherein the first nanosheet stack includes a plurality of first nanosheet layers, wherein the each of the plurality of first channel layers are spaced apart from each other a first distance;
a second nanosheet stack for a second device of a second channel type different from the first channel type, wherein the second nanosheet stack includes a plurality of second nanosheet layers, wherein the second nanosheet stack is disposed on top of the first nanosheet stack, wherein each of the plurality of second channel layers are spaced apart a second distance, wherein the first distance is less than the second distance; and
a gate structure wrapping around the first nanosheet stack and the second nanosheet stack, wherein the gate structure comprises
a gate dielectric layer surrounding a first set of nanosheet layers of the first nanosheet stack and a second set of nanosheet layers of the second nanosheet stack;
a first work function layer is located between two different portions of the gate dielectric layer located in the first nanosheet stack, wherein the first work function layer is in direct contact with the gate dielectric that surrounds each of the plurality of first nanosheet layers;
a second work function layer in contact with at least second portion of the gate dielectric layer surrounding the second set of nanosheet layers, wherein the second work function layer is in direct contact with the gate dielectric layer that surrounds the plurality of second channel layers, wherein the first work function layer is not in contact with the gate dielectric layer that surrounds the plurality of second channel layers, wherein a gap exists between portions of the second work function layer between each nanosheet layer of the second set of nanosheet layers; and
a gate conductor layer formed in contact with the second work function layer, wherein the gate conductor layer fills the gap between the portions of the second work function layer.
2. The semiconductor device of claim 1 , further comprising:
a first source layer and a first drain layer of the first doping type formed in contact with the first nanosheet stack;
a dielectric layer formed top of and in contact with at least the first source layer and the first drain layer; and
a second source layer and a second drain layer of the second doping type formed in contact with the second nanosheet stack and further formed in contact with a top surface of the dielectric layer.
3. The semiconductor device of claim 1 , wherein the first work function layer comprises a different material than the second work function layer.
4. A semiconductor device comprising at least:
a first nanosheet stack for a first device of a first channel type, wherein the first nanosheet stack includes a plurality of first nanosheet layers, wherein the each of the plurality of first channel layers are spaced apart from each other a first distance;
a second nanosheet stack for a second device of a second channel type different from the first channel type, wherein the second nanosheet stack includes a plurality of second nanosheet layers, wherein the second nanosheet stack is disposed on top of the first nanosheet stack, wherein each of the plurality of second channel layers are spaced apart a second distance, wherein the first distance is less than the second distance; and
a gate structure wrapping around the first nanosheet stack and the second nanosheet stack, wherein the gate structure comprises
a gate dielectric layer;
a first work function layer is located between two different portions of the gate dielectric layer located in the first nanosheet stack, wherein the first work function layer is in direct contact with the gate dielectric that surrounds each of the plurality of first nanosheet layers;
a second work function layer in contact with at least second portion of the gate dielectric layer surrounding nanosheet layers of the second nanosheet stack, wherein the second work function layer is in direct contact with the gate dielectric layer that surrounds the plurality of second channel layers, wherein the first work function layer is not in contact with the gate dielectric layer that surrounds the plurality of second channel layers; and
a gate conductor layer formed in contact with the second work function layer.
5. The semiconductor device of claim 4 , wherein the first work function layer is pinched off between each nanosheet layer of the plurality of first nanosheet layers.
6. The semiconductor device of claim 4 , wherein the gate conductor layer fills a gap between portions of the second work function layer between each of the plurality of second nanosheet layers of the second nanosheet stack.