Nonvolatile memory device and method for fabricating the same
A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
1. A three-dimensional semiconductor device comprising:
a first alternating stack of first dielectric layers and first electrically conductive layers on a substrate;
a second alternating stack of at least one second dielectric layer and at least one second electrically conductive layer on the first alternating stack;
a memory cell region including a plurality of channel hole structures that vertically extend through each layer of the first alternating stack and the second alternating stack;
a contact region including first stepped surfaces of the first alternating stack and a second stepped surface of the second alternating stack; and
a plurality of dielectric supporter structures including a dielectric material, and extending through the first alternating stack,
wherein the plurality of dielectric supporter structures are laterally spaced apart from the at least one second dielectric layer and the at least one second electrically conductive layer.
2. The three-dimensional semiconductor device of claim 1 , further comprising a dielectric region on the first stepped surfaces,
wherein the plurality of dielectric supporter structures extend through the dielectric region.
3. The three-dimensional semiconductor device of claim 2 , wherein each of the plurality of dielectric supporter structures protrudes above the first stepped surfaces and includes an upper portion that is laterally surrounded by the dielectric region.
4. The three-dimensional semiconductor device of claim 2 , further comprising:
a plurality of first word line contacts, each of the plurality of first word line contacts extending through the dielectric region and contacting a corresponding one of the first electrically conductive layers.
5. The three-dimensional semiconductor device of claim 2 ,
wherein the dielectric region continuously extends from a surface of a bottommost first dielectric layer of the first alternating stack to a level of a surface of a topmost second dielectric layer of the second alternating stack,
wherein the dielectric region is a single-layer region, and
wherein the dielectric region laterally surrounds the plurality of dielectric supporter structures.
6. The three-dimensional semiconductor device of claim 1 , wherein each of the plurality of dielectric supporter structures has a top surface coplanar with a topmost layer of the second alternating stack.
7. The three-dimensional semiconductor device of claim 1 ,
wherein bottom surfaces of the plurality of dielectric supporter structures are coplanar with each other, and
wherein bottom portions of the plurality of channel hole structures contact an impurity region that underlies the bottom surfaces of the plurality of dielectric supporter structures.
8. The three-dimensional semiconductor device of claim 1 , wherein each of the plurality of channel hole structures includes a charge storage layer and an active structure.
9. The three-dimensional semiconductor device of claim 8 , wherein the charge storage layer includes a charge tunneling layer.
10. A three-dimensional semiconductor device comprising:
a first alternating stack of first dielectric layers and first electrically conductive layers on a substrate;
a second alternating stack of at least one second dielectric layer and at least one second electrically conductive layer on the first alternating stack;
a memory cell region including a plurality of channel hole structures that vertically extend through each layer of the first alternating stack and the second alternating stack;
a contact region including first stepped surfaces of the first alternating stack and a second stepped surface of the second alternating stack;
a plurality of dielectric supporter structures including a dielectric material, and extending through the first alternating stack; and
a dielectric region on the first stepped surfaces,
wherein the dielectric region continuously extends from a surface of a bottommost first dielectric layer of the first alternating stack to a level of a surface of a topmost second dielectric layer of the second alternating stack,
wherein the dielectric region is on sidewalls of the plurality of dielectric supporter structures, and
wherein the plurality of dielectric supporter structures are laterally spaced apart from the at least one second dielectric layer and the at least one second electrically conductive layer.
11. The three-dimensional semiconductor device of claim 10 , wherein the dielectric region is a single-layer region.
12. The three-dimensional semiconductor device of claim 10 , wherein each of the plurality of dielectric supporter structures protrudes above the first stepped surfaces and includes an upper portion that is laterally surrounded by the dielectric region.