Fabrication method for a 3-dimensional NOR memory array

1. A process for forming a memory structure over a planar surface of a semiconductor substrate, comprising:

forming above the semiconductor substrate a plurality of active stacks placed substantially at predetermined positions along a first direction that is substantially parallel to the planar surface, separated one from another by a first electrically insulative material, each active stack extending lengthwise along a second direction that is (i) substantially parallel to the planar surface and (ii) substantially orthogonal the first direction, wherein (i) each active stack comprises a plurality of active strips, provided along at predetermined positions along a third direction that is substantially orthogonal to the planar surface, each active strip being separated one from another by a first isolation layer; and (ii) each active strip comprises (a) first and second semiconductor layers of a first conductivity type, and (b) a second isolation layer separating the first and the second semiconductor layers;

patterning and etching the first electrically insulative material to provide a plurality of openings at predetermined positions along the first direction, the openings each extending along the third direction, exposing sidewalls of the active stacks on opposite sides of the opening;

etching the second isolation layer of each active strip through the openings, thereby creating recesses between the first and the second semiconductor layers at opposite sides of the second isolation layer;

conformally depositing a third semiconductor layer, the third semiconductor layer being of a second conductivity opposite the first conductivity, such that the third semiconductor layer lines the sidewalls of the opening and one or more walls of the recesses of each active strip;

anisotropically etching the third semiconductor layer to remove the third semiconductor layer from the sidewalls of the openings;

conformally depositing a charge-trapping material on the sidewalls of the opening, such that the third semiconductor layer in the recesses are in contact with the charge-trapping layer; and

filling the openings with a conductive material.

2. The process of claim 1 , wherein each active strip further comprises a sacrificial layer provided adjacent each of the first and the second semiconductor layers on the side of the corresponding semiconductor layer obverse to the second isolation layer, the process further comprising replacing the sacrificial layer by a conductive layer.

3. The process of claim 2 , wherein the conductive layer comprises a barrier layer and a metallic layer comprising a refractory metal.

4. The process of claim 3 , wherein the barrier layer comprises tungsten nitride or titanium nitride.

5. The process of claim 4 , wherein the refractory metal comprises tungsten.

6. The process of claim 2 , wherein replacing the sacrificial layer comprises isotropically etching the sacrificial layer from each of the openings using an etchant that is selective to the first electrically insulative material.

7. The process of claim 2 , wherein replacing the sacrificial material is carried out prior to isotropically etching the second isolation layer of each active strip and wherein the process further comprising removing substantially all the first electrically insulative material prior to etching the second isolation layer.

8. The process of claim 7 , wherein the second isolation layer comprises a second electrically insulative material, and wherein removing substantially all the first electrically insulative material comprises replacing the first electrically insulative material by a significantly less quantity of the second electrically insulative material, such that the openings are substantially enlarged.

9. The process of claim 1 , wherein the second isolation layer comprises the first electrically insulative material, such that etching the second isolation layer also removes a portion of the first insulative material from the sidewall a of the opening.

10. The process of claim 1 , wherein the first electrically insulative material comprises silicon oxide.

11. The process of claim 1 , wherein the first isolation layer comprises silicon oxycarbon (SiOC).

12. The process of claim 1 wherein the second isolation layer comprises silicon oxide.

13. The process of claim 1 , wherein the third semiconductor layer comprises an in situ-doped polysilicon.

14. The process of claim 1 , wherein the third semiconductor layer has a dopant concentration that is lower than the dopant concentration of either the first semiconductor layer or the dopant concentration of the second semiconductor layer.

15. The process of claim 1 , wherein conformally depositing the charge-trapping layer comprises depositing a tunnel dielectric layer a silicon-rich nitride, and a blocking dielectric layer.

16. The process of claim 15 , wherein the blocking dielectric layer comprises an aluminum oxide layer.

17. The process of claim 1 , wherein the conductive material comprises heavily-doped polysilicon.

18. The process of claim 1 , further comprising forming conductors above the memory structure, each conductor extending along the second direction and in electrical contact with conductive material at predetermined locations.

19. The process of claim 1 , wherein each active strip forms one or more NOR memory strings.

20. The process of claim 19 wherein, within each NOR memory strings comprises a plurality of storage transistors, and wherein the first and the second semiconductor layers provide a common drain region and a common source region, respectively.

21. The process of claim 20 , wherein the third semiconductor layer provides for each storage transistor a channel region.