Stacked field effect transistor with wrap-around contacts
Embodiments of the present invention are directed to a method for forming a complementary field effect transistor (CFET) structure having a wrap-around contact. In a non-limiting embodiment of the invention, a complementary nanosheet stack is formed over a substrate. The complementary nanosheet stack includes a first nanosheet and a second nanosheet separated by a dielectric spacer. A first sacrificial layer is formed over a source or drain (S/D) region of the first nanosheet and a second sacrificial layer is formed over a S/D region of the second nanosheet. A conductive gate is formed over channel regions of the first nanosheet and the second nanosheet. After the conductive gate is formed, the first sacrificial layer is replaced with a first wrap-around contact and the second sacrificial layer is replaced with a second wrap-around contact.
1. A semiconductor device comprising:
a nanosheet stack over a substrate, the nanosheet stack comprising a top portion and a bottom portion separated by a dielectric spacer;
a plurality of vertically stacked first source or drain (S/D) regions, each of the first S/D regions on a sidewall of a different nanosheet in the bottom portion of the nanosheet stack, each of the first S/D regions confined to the respective sidewall of one nanosheet such that none of the plurality of first S/D regions merge and each sidewall of the different nanosheets in the bottom portion is covered by a separate first S/D region;
a plurality of vertically stacked second S/D regions, each of the second S/D regions on a sidewall of a different nanosheet in the top portion of the nanosheet stack, each of the second S/D regions confined to the respective sidewall of one nanosheet such that none of the plurality of second S/D regions merge and each sidewall of the different nanosheets in the top portion is covered by a separate second S/D region;
a first wrap-around contact formed over the first plurality of S/D regions; and
a second wrap-around contact formed over the second plurality of S/D regions.
2. The semiconductor device of claim 1 , wherein the top portion is an n-type portion and the bottom portion is a p-type portion.
3. The semiconductor device of claim 1 , wherein the top portion is a p-type portion and the bottom portion is an n-type portion.
4. The semiconductor device of claim 1 , wherein the first wrap-around contact is horizontally offset from the second wrap-around contact.
5. A semiconductor device comprising:
a first nanosheet stack over a substrate, the first nanosheet stack comprising a first nanosheet;
a second nanosheet stack over the first nanosheet stack, the second nanosheet stack comprising a second nanosheet;
first source and drain regions on sidewalls of the first nanosheet, the first source and drain regions comprising a first dopant, the first source and drain regions confined to the respective sidewalls of the first nanosheet such that the first source and drain regions do not merge with other source and drain regions on respective other nanosheets in the first nanosheet stack;
second source and drain regions on sidewalls of the second nanosheet, the second source and drain regions comprising a second dopant having an opposite doping type from the first dopant, the second source and drain regions confined to the respective sidewalls of the second nanosheet such that the second source and drain regions do not merge with other source and drain regions on respective other nanosheets in the second nanosheet stack;
an isolation dielectric between the first source and drain regions and the second source and drain regions;
a first wrap-around contact formed over the first source and drain regions, the first wrap-around contact in direct contact with a bottommost surface of the isolation dielectric; and
a second wrap-around contact formed over the second source and drain regions, the second wrap-around contact in direct contact with a topmost surface of the isolation dielectric.
6. The semiconductor device of claim 5 , wherein the first dopant comprises an n-type dopant and the second dopant comprises a p-type dopant.
7. The semiconductor device of claim 5 , wherein the second dopant comprises an n-type dopant and the first dopant comprises a p-type dopant.
8. The semiconductor device of claim 5 further comprising a dielectric spacer between the first nanosheet stack and the second nanosheet stack.