Semiconductor device with embedded magnetic storage structure and method for fabricating the same
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of nanowires positioned above and parallel to a top surface of the substrate, wherein the plurality of nanowires comprises channel regions and source/drain regions positioned on each of both sides of the channel regions; a gate stack positioned surrounding the channel regions; and a magnetic storage structure positioned above a drain region of the plurality of nanowires and positioned adjacent to the gate stack. The magnetic storage structure comprises a bottom ferromagnetic layer positioned above the drain region and having a variable magnetic polarity, a tunnel barrier layer positioned on the bottom ferromagnetic layer, and a top ferromagnetic layer positioned on the tunnel barrier layer and having a fixed magnetic polarity.
1. A semiconductor device, comprising:
a substrate;
a plurality of nanowires positioned above and parallel to a top surface of the substrate, wherein the plurality of nanowires comprises channel regions and source/drain regions positioned on each of both sides of the channel regions;
a gate stack positioned surrounding the channel regions;
a magnetic storage structure positioned above the drain region of the plurality of nanowires and positioned adjacent to the gate stack, wherein the magnetic storage structure comprises a bottom ferromagnetic layer positioned above the drain region and having a variable magnetic polarity, a tunnel barrier layer positioned on the bottom ferromagnetic layer, and a top ferromagnetic layer positioned on the tunnel barrier layer and having a fixed magnetic polarity, wherein the plurality of nanowires are arranged vertically;
a bottom electrode positioned below the bottom ferromagnetic layer and positioned adjacent to the gate stack, wherein a width of the bottom electrode is greater than a width of the bottom ferromagnetic layer, wherein a thickness of the bottom ferromagnetic layer is between about 8 angstroms and about 13 angstroms;
two storage spacers positioned on two sides of the top ferromagnetic layer, two sides of the tunnel barrier layer, and two sides of the bottom ferromagnetic layer; and
two contacts positioned on two sides of the gate stack and surrounding the source/drain regions of the plurality of nanowires.
2. The semiconductor device of claim 1 , further comprising two gate spacers positioned between the two contacts and the gate stack, and a thickness of the tunnel barrier layer is between about 0.5 nanometer and about 2.0 nanometers.
3. The semiconductor device of claim 2 , further comprising a plurality of coverage layers positioned between the channel regions of the plurality of nanowires and the gate stack, wherein a band gap of the plurality of coverage layers is smaller than a band gap of the plurality of nanowires.