IP Library › Patent Application 17516688
Patent Application
App. No. 17/516,688

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH POROUS DIELECTRIC STRUCTURE

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Quick Facts
Patent No.
US None
App. No.
17/516,688
Abstract

The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate; forming two conductive features apart from each other over the substrate; forming a porous middle layer positioned between the two conductive features and adjacent to the two conductive features; depositing an energy-removable material between the two conductive features and adjacent to the two conductive features; and performing an energy treatment to transform the energy-removable material into a porous middle layer. The porosity of the porous middle layer is between about 25% and about 100%.

Claims (12)

1 . A method for fabricating a semiconductor device, comprising:

providing a substrate;

forming two conductive features apart from each other over the substrate;

forming a porous middle layer positioned between the two conductive features and adjacent to the two conductive features;

depositing an energy-removable material between the two conductive features and adjacent to the two conductive features; and

performing an energy treatment to transform the energy-removable material into a porous middle layer;

wherein a porosity of the porous middle layer is between about 25% and about 100%.

2 . The method for fabricating the semiconductor device of claim 1 , wherein the energy-removable material comprises a base material and a decomposable porogen material.

3 . The method for fabricating the semiconductor device of claim 2 , wherein an energy source of the energy treatment is heat, light, or a combination thereof.

4 . The method for fabricating the semiconductor device of claim 3 , wherein the base material comprises methylsilsesquioxane or silicon oxide.

5 . The method for fabricating the semiconductor device of claim 4 , further comprising forming a first stop layer on the substrate, wherein the first stop layer has a thickness between about 1 nm and about 50 nm.

6 . The method for fabricating the semiconductor device of claim 5 , further comprising forming a plurality of fins on the first stop layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2021
From: TSAI, HUNG-CHI
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 057987/0776 →