IP Library › Granted Patent US 12,096,633
Granted Patent B2
US 12,096,633 · App. 17/517,459 · Granted Sep 17, 2024

Memory arrays and methods used in forming a memory array comprising strings of memory cells

Inventors: Jordan D. Greenlee (Boise, ID); Daniel Billingsley (Meridian, ID); Indra V. Chary (Boise, ID); Rita J. Klein (Boise, ID)
H10B43/27H01L21/02164H01L21/0217H01L21/02636H01L21/31111H10B41/10H10B41/27H10B43/10H01L29/66545
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Quick Facts
Patent No.
US 12,096,633
App. No.
17/517,459
Granted
Sep 17, 2024
Kind
B2
Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.

Claims (17)

1. A method used in forming a memory array comprising strings of memory cells, comprising:

forming a stack comprising vertically-alternating first tiers and second tiers;

forming horizontally-elongated trenches into the stack to form laterally-spaced memory-block regions; and

forming upper masses across and along the horizontally-elongated trenches to be laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory-block regions, void space being below the upper masses in the horizontally-elongated trenches between the laterally-spaced memory-block regions.

2. The method of claim 1 comprising filling the void space with insulative material.

3. The method of claim 1 wherein forming the upper masses comprises:

forming lower material in the horizontally-elongated trenches;

vertically-recessing longitudinally-spaced regions of the lower material to form vertical recesses;

filling the vertical recesses with upper material that is of different composition from that of the lower material; and

selectively etching the lower material relative to the upper material to leave the upper material to be said upper masses.

4. The method of claim 1 comprising, through spaces that are longitudinally-between the upper masses, isotropically etching away and replacing sacrificial material that is in the first tiers with conducting material of individual conductive lines.

5. The method of claim 1 comprising forming individual memory cells of the strings of memory cells to comprise channel material of operative channel-material strings, a gate region that is part of a conductive line in individual of the first tiers, and a memory structure laterally-between the gate region and the channel material of the operative channel-material strings in the individual first tiers, conducting material of the first tiers being formed after forming the upper masses.

6. The method of claim 1 comprising forming individual memory cells of the strings of memory cells to comprise channel material of operative channel-material strings, a gate region that is part of a conductive line in individual of the first tiers, and a memory structure laterally-between the gate region and the channel material of the operative channel-material strings in the individual first tiers, conducting material of the first tiers being formed before forming the horizontally-elongated trenches.

7. A method used in forming a memory array comprising strings of memory cells, comprising:

forming a stack comprising vertically-alternating first tiers and second tiers;

forming horizontally-elongated trenches into the stack to form laterally-spaced memory-block regions; and

forming pillars laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks, the pillars comprising an upper first material and a second material below the first material, the first and second materials being of different compositions relative one another.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 065166/0674 →
Continuity (2)
Division 16550250 · Aug 25, 2019
Related Publication 20220059569A1 · Feb 24, 2022