Circuits and methods for correcting errors in memory
An electronic system includes a processor circuit, a memory circuit, and an error correction circuit. The error correction circuit receives information read from the memory circuit. The error correction circuit detects if the information contains an error. The error correction circuit corrects the error in the information to generate corrected information and provides the corrected information and an error signal to the processor circuit. The processor circuit provides the corrected information and a write command to the memory circuit based on the error signal indicating the error. The memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command.
1 . An integrated circuit comprising:
a read and write circuit;
a memory circuit; and
an error correction circuit that:
receives information read from the memory circuit,
generates an error signal indicating if the information contains an error,
determines whether the error in the information read from the memory circuit is correctable,
in response to the determination that the error is uncorrectable:
causes a processor circuit to shut down or reset, and
in response to the determination that the error is correctable:
corrects the error in the information to generate corrected information, and
provides the corrected information to the read and write circuit, and
wherein the read and write circuit causes the memory circuit to overwrite the information stored in the memory circuit with the corrected information in response to the error signal, wherein the processor circuit comprises the read and write circuit, and wherein the processor circuit temporarily stalls execution of a program without saving state information of the processor circuit while the corrected information is stored in the memory circuit.
2 . The integrated circuit of claim 1 , wherein the read and write circuit comprises a multiplexer circuit that provides the corrected information to the memory circuit to overwrite the information stored in the memory circuit in response to the error signal indicating that the information contains a correctable error.
3 . The integrated circuit of claim 2 , wherein the information read from the memory circuit is data, and wherein the corrected information generated by the error correction circuit is corrected data.
4 . The integrated circuit of claim 1 , wherein the read and write circuit provides a write command to the memory circuit in response to the error signal indicating that the information contains a correctable error, and wherein the memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command from the read and write circuit.
5 . The integrated circuit of claim 1 , wherein the read and write circuit provides the error signal to the memory circuit, and wherein the memory circuit stores the corrected information in the memory circuit in response to the error signal indicating that the information contains a correctable error.
6 . The integrated circuit of claim 5 , wherein the information read from the memory circuit is an instruction, and wherein the corrected information generated by the error correction circuit is a corrected instruction.
7 . The integrated circuit of claim 1 , wherein the integrated circuit is a programmable integrated circuit, and wherein the read and write circuit and the error correction circuit are implemented by programmable logic circuits.
8 . The integrated circuit of claim 1 , wherein the error correction circuit generates multiple error signals indicating whether the information read from the memory circuit contains the error and whether the error is correctable or uncorrectable.
9 . A method for overwriting information stored in a memory circuit, the method comprising:
receiving the information read from the memory circuit at an error correction circuit;
generating an error signal indicating if the error correction circuit has detected an error in the information;
determining whether the error in the information is correctable;
in response to determining that the error is uncorrectable:
causing a processor circuit to shut down or reset; and
in response to determining that the error is correctable:
correcting the error in the information using the error correction circuit to generate corrected information if the error is a correctable error;
providing the corrected information and the error signal to the processor circuit;
providing the corrected information and a write command to the memory circuit when the error signal indicates the error using the processor circuit;
temporarily stalling execution of a program running in the processor circuit without saving states of the processor circuit; and
while execution of the program is temporarily stalled, overwriting the information stored in the memory circuit with the corrected information in response to the write command.
10 . The method of claim 9 , wherein providing the corrected information and the write command to the memory circuit further comprises providing the corrected information to the memory circuit using a multiplexer circuit in response to the error signal indicating that the information contains the correctable error.
11 . The method of claim 10 , wherein providing the corrected information to the memory circuit using the multiplexer circuit further comprises:
prioritizing providing the corrected information to the memory circuit over an additional command from the processor circuit using the multiplexer circuit.
12 . The method of claim 9 , wherein providing the corrected information and the write command to the memory circuit further comprises providing the error signal to the memory circuit using the processor circuit, and
wherein overwriting the information stored in the memory circuit with the corrected information further comprises storing the corrected information in the memory circuit in response to the error signal indicating that the information contains the correctable error.
13 . An electronic system comprising:
a processor circuit;
a memory circuit; and
an error correction circuit that:
receives information read from the memory circuit,
detects whether the information contains an error,
determines whether the error in the information read from the memory circuit is correctable,
in response to the determination that the error is uncorrectable:
causes the processor circuit to shut down or reset; and
in response to the determination that the error is correctable:
corrects the error in the information to generate corrected information, and
provides the corrected information and an error signal to the processor circuit, and
wherein:
the processor circuit provides the corrected information and a write command to the memory circuit based on the error signal indicating the error;
the processor circuit temporarily stalls execution of a program without saving states of the processor circuit; and
while execution of the program is temporarily stalled, the memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command.
14 . The electronic system of claim 13 , wherein the processor circuit comprises a multiplexer circuit that provides the corrected information to the memory circuit to overwrite the information stored in the memory circuit in response to the error signal indicating that the information contains a correctable error, and wherein the multiplexer circuit prioritizes providing the corrected information to the memory circuit over an additional command from the processor circuit.
15 . The electronic system of claim 13 , wherein the processor circuit provides the error signal to the memory circuit, and wherein the memory circuit stores the corrected information in the memory circuit in response to the error signal provided from the processor circuit indicating that the information contains a correctable error.
16 . The electronic system of claim 13 , wherein the information is accessed from the memory circuit in response to a read command provided to the memory circuit from a read and write circuit in the processor circuit.