IP Library Granted Patent US 12,346,726
Granted Patent B2
US 12,346,726 · App. 17/529,854 · Granted Jul 1, 2025

Task scheduling method, and computing device and application processor using the same

Inventors: Seyeong Byeon (Suwon-si, KR); Jonglae Park (Anyang-si, KR); Hojin Kim (Seoul, KR); Gurnrack Moon (Seoul, KR); Daeyeong Lee (Seongnam-si, KR); Youngtae Lee (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F9/4881G06F9/505G06F9/5088
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,346,726
App. No.
17/529,854
Granted
Jul 1, 2025
Kind
B2
Abstract

A task scheduling method for a central processing unit (CPU) including a plurality of cores includes receiving a task processing request, obtaining first feedback data for the plurality of cores, obtaining second feedback data for an external intellectual property (IP) block outside the CPU, and assigning a task to at least one of the plurality of cores based on the first feedback data and the second feedback data.

Claims (83)

1. A task scheduling method for a central processing unit (CPU) including a plurality of cores and a scheduler, the task scheduling method comprising:

receiving, by the scheduler of the CPU, a task processing request;

obtaining, by the scheduler of the CPU, first feedback data for the plurality of cores;

obtaining, by the scheduler of the CPU, second feedback data for an external intellectual property (IP) block outside the CPU, wherein the second feedback data are received from the external IP block;

generating, by a sub-scheduler module of the scheduler of the CPU, reference data comprising a performance requirement based on the second feedback data; and

assigning, by a main scheduler module of the scheduler of the CPU, a task to at least one of the plurality of cores based on the first feedback data and the reference data.

2. The task scheduling method of claim 1 , further comprising:

performing the task by the at least one of the plurality of cores and generating a task processing result; and

performing, by at least one IP block of the external IP block, subsequent processing of the task.

3. The task scheduling method of claim 2 ,

wherein the external IP block comprises at least one of a graphics processing unit (GPU) and a display device, and

wherein the second feedback data comprises at least one of feedback data for the GPU and feedback data for the display device.

4. The task scheduling method of claim 3 ,

wherein the second feedback data for the GPU comprises information about at least one of a use rate, a temperature, and performance of the GPU, and

wherein the second feedback data for the display device comprises information about frames per second (fps) of the display device.

5. The task scheduling method of claim 1 ,

wherein the obtaining of the second feedback data comprises periodically receiving the second feedback data from the external IP block.

6. The task scheduling method of claim 1 ,

wherein the first feedback data comprises utilization of each of the plurality of cores, and

wherein the utilization indicates a degree of use of each of the plurality of cores.

7. The task scheduling method of claim 6 ,

wherein the assigning of the task to the at least one of the plurality of cores comprises:

assigning the task to a first core of the plurality of cores based on the first feedback data; and

correcting the assigning of the task to the first core based on the second feedback data.

8. The task scheduling method of claim 7 ,

wherein the correcting of the assigning of the task to the first core comprises:

if the first core is determined as not meeting the performance requirement and a second core of the plurality of cores meets the performance requirement, assigning the task to the second core of the plurality of cores.

9. The task scheduling method of claim 6 ,

wherein the assigning of the task to the at least one of the plurality of cores comprises:

checking whether the plurality of cores include a first core meeting the performance requirement based on the first feedback data;

assigning the task to the first core; and

transmitting the task to the first core.

10. The task scheduling method of claim 1 ,

wherein the plurality of cores comprise a first core, a second core, and a third core, and

wherein the first core, the second core, and the third core are different from each other in a degree of performance.

11. A computing device comprising:

a plurality of cores; and

a control unit configured to control an operation of the computing device,

wherein the control unit is further configured to:

receive a task processing request for a first task;

obtain first feedback data for the plurality of cores;

obtain second feedback data for at least one of a graphics processing unit (GPU) and a display device, wherein the control unit receives the second feedback data from the at least one of the GPU and the display device; and

assign the first task to at least one of the plurality of cores based on the first feedback data and reference data, and

wherein the control unit comprises:

a main scheduler module configured to assign the first task to the at least one of the plurality of cores; and

a sub-scheduler module configured to generate the reference data comprising a performance requirement based on the second feedback data.

12. The computing device of claim 11 ,

wherein the second feedback data for the GPU comprises information about at least one of a use rate, a temperature, and performance of the GPU, and

wherein the second feedback data for the display device comprises information about frames per second (fps) of the display device.

13. The computing device of claim 11 ,

wherein the main scheduler module is further configured to:

receive the reference data from the sub-scheduler module; and

assign the first task to the at least one of the plurality of cores based on the reference data and the first feedback data.

14. The computing device of claim 11 ,

wherein the main scheduler module is further configured to:

receive the reference data from the sub-scheduler module;

assign the first task to a first core of the plurality of cores based on the first feedback data; and

if the first core is determined as not meeting the performance requirement, assign the first task to a second core of the plurality of cores based on the reference data.

15. The computing device of claim 11 ,

wherein the sub-scheduler module is further configured to:

determine whether the performance requirement of the reference data requires a higher level of performance than a preset performance requirement to generate a determination result; and

transmit the reference data to the main scheduler module according to the determination result.

16. The computing device of claim 15 ,

wherein the sub-scheduler module is further configured:

to transmit the reference data to the main scheduler module if the performance requirement of the reference data requires a higher level of performance than the preset performance requirement; and

not to transmit the reference data to the main scheduler module if the performance requirement of the reference data does not require a higher level of performance than the preset performance requirement.

17. The computing device of claim 11 ,

wherein the first feedback data comprises utilization of each of the plurality of cores.

18. The computing device of claim 11 ,

wherein the plurality of cores comprise a first core, a second core, and a third core, and

wherein the first core, the second core, and the third core are different from each other in a degree of performance.

19. An application processor comprising:

a central processing unit (CPU) comprising a plurality of cores;

a computing resource outside the CPU; and

a display interface configured to communicate with a display device outside the application processor,

wherein the CPU is configured to:

receive a task processing request for a first task;

obtain first feedback data for the plurality of cores;

obtain second feedback data for the computing resource and the display device functionally connected through the display interface, wherein the CPU receives the second feedback data from the computing resource and from the display device through the display interface; and

assign the first task to one of the plurality of cores based on the first feedback data and reference data, and

wherein the CPU comprises:

a main scheduler module configured to assign the first task to the one of the plurality of cores; and

a sub-scheduler module configured to generate the reference data comprising a performance requirement based on the second feedback data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2021
From: BYEON, SEYEONG; PARK, JONGLAE; KIM, HOJIN; MOON, GURNRACK; LEE, DAEYEONG; LEE, YOUNGTAE
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 058453/0046 →
Priority Claims (2)
KR 10-2021-0040544 · Mar 29, 2021 · national
KR 10-2021-0061642 · May 12, 2021 · national
Continuity (1)
Related Publication 20220308920A1 · Sep 29, 2022
References Cited (35)
US 8217951B2 · Jung · 2012 [cited by applicant]
US 9311157B2 · Kim et al. · 2016 [cited by applicant]
US 9354944B2 · Gaster et al. · 2016 [cited by applicant]
US 9378533B2 · Ro · 2016 [cited by examiner]
US 9626295B2 · Park · 2017 [cited by examiner]
US 10186007B2 · Barik et al. · 2019 [cited by applicant]
US 10345850B2 · Jang · 2019 [cited by examiner]
US 10430915B2 · Khodakovsky et al. · 2019 [cited by applicant]
US 20080165198A1 · Bakalash · 2008 [cited by examiner]
US 20100162253A1 · Jeong · 2010 [cited by examiner]
US 20120188259A1 · Hartog · 2012 [cited by examiner]
US 20130247068A1 · Min · 2013 [cited by examiner]
US 20140259022A1 · Jung · 2014 [cited by applicant]
US 20150067700A1 · Kim · 2015 [cited by examiner]
US 20160004564A1 · Park · 2016 [cited by examiner]
US 20160055612A1 · Barik · 2016 [cited by examiner]
US 20160358537A1 · Kang · 2016 [cited by examiner]
US 20170024316A1 · Park · 2017 [cited by examiner]
US 20170090988A1 · Young · 2017 [cited by examiner]
US 20170148417A1 · Lee · 2017 [cited by examiner]
US 20170212575A1 · Wang · 2017 [cited by examiner]
US 20180276044A1 · Fong · 2018 [cited by examiner]
US 20180373564A1 · Hushchyn · 2018 [cited by examiner]
US 20190087225A1 · Rozen · 2019 [cited by examiner]
US 20190205170A1 · Hushchyn · 2019 [cited by examiner]
US 20190332157A1 · Hsu · 2019 [cited by examiner]
US 20200043123A1 · Dash · 2020 [cited by examiner]
US 20200151008A1 · Hilton · 2020 [cited by examiner]
US 20200184366A1 · Mandal · 2020 [cited by examiner]
US 20200371838A1 · Mandal · 2020 [cited by examiner]
US 20210018971A1 · Rotem · 2021 [cited by examiner]
US 20210026696A1 · Chen et al. · 2021 [cited by applicant]
US 20210334703A1 · Salamat · 2021 [cited by examiner]
US 20220035665A1 · Foukas · 2022 [cited by examiner]
KR 101953906B1 · 2019 [cited by applicant]