Methods and systems configured to specify resources for hyperdimensional computing implemented in programmable devices using a parameterized template for hyperdimensional computing

1. A method of defining an implementation of circuits in a programmable device, the method comprising:

receiving a plurality of specifications for a hyperdimensional (HD) computing machine learning application for execution on a programmable device;

determining parameters for a template architecture for HD computing machine learning using the plurality of specifications, the template architecture including an HD hypervector encoder, an HD associative search unit, programmable device pre-defined processing units, and programmable device pre-defined processing elements within the pre-defined processing units; and

generating programmable device code configured to specify resources to be allocated within the programmable device using pre-defined circuits defined for use in the programmable device using the determined parameters for the template architecture,

wherein the template architecture supports concurrent execution of training and inference operations by dynamically allocating programmable device resources in response to real-time operational requirements, and wherein the programmable device code comprises instructions for reconfiguring the programmable device by adjusting the allocation and utilization of the programmable device resources in response to changes in an operational state of the HD computing machine learning application.

2. The method of claim 1 further comprising:

defining a controller for operation within the programmable device configured to coordinate operations of the HD computing machine learning application implemented within the programmable device according to the programmable device.

3. The method of claim 1 , wherein the HD hypervector encoder converts data inputs into HD vectors for processing in the HD computing machine learning application.

4. The method of claim 3 , wherein the HD associative search unit performs search operations within the HD vectors to identify relevant data.

5. The method of claim 1 , where the programmable device code generated for the programmable device specifies which resources are to be allocated to each of the pre-defined circuits.

6. The method of claim 1 , wherein the programmable device is configurable for different HD computing machine learning applications by changing the plurality of specifications and parameters for the template architecture.

7. The method of claim 1 , wherein the programmable device is capable of being updated and reconfigured over time to improve its performance in executing HD computing machine learning applications.

8. The method of claim 1 , further comprising:

designing a circuit implementation plan based on the determined parameters for the template architecture;

generating the programmable device code using the circuit implementation plan; and

integrating the programmable device code into the programmable device to implement the circuits required for the HD computing machine learning application.

9. The method of claim 1 , wherein the changes in the operational state of the hyperdimensional (HD) computing machine learning application include transitions between training, inference, and retraining modes.

10. The method of claim 1 , further comprising:

configuring the HD hypervector encoder included in the template architecture to perform real-time conversion of incoming data streams into HD vectors, wherein the real-time conversion process is optimized based on the real-time operational requirements of the HD computing machine learning application, and

configuring the HD associative search unit included in the template architecture to dynamically prioritize search operations within the HD vectors during the concurrent execution of training and inference operations, wherein the prioritization is adjusted based on current allocation of programmable device resources.

11. Non-transitory computer readable media comprising computer-executable instructions that, when executed by a computing system, cause the computing system to:

receive a plurality of specifications for a hyperdimensional (HD) computing machine learning application for execution on a programmable device;

determine parameters for a template architecture for HD computing machine learning using the plurality of specifications, the template architecture including an HD hypervector encoder, an HD associative search unit, programmable device pre-defined processing units, and programmable device pre-defined processing elements within the pre-defined processing units; and

generate programmable device code configured to specify resources to be allocated within the programmable device using pre-defined circuits defined for use in the programmable device using the determined parameters for the template architecture,

wherein the template architecture supports concurrent execution of training and inference operations by dynamically allocating programmable device resources in response to real-time operational requirements, and wherein the programmable device code comprises instructions for reconfiguring the programmable device by adjusting the allocation and utilization of the programmable device resources in response to changes in an operational state of the HD computing machine learning application.

12. The non-transitory computer readable media of claim 11 , wherein execution of the computer-executable instructions further cause the computing system to:

define a controller for operation within the programmable device configured to coordinate operations of the HD computing machine learning application implemented within the programmable device according to the programmable device.

13. The non-transitory computer readable media of claim 11 , wherein the HD hypervector encoder converts data inputs into HD vectors for processing in the HD computing machine learning application.

14. The non-transitory computer readable media of claim 13 , wherein the HD associative search unit performs search operations within the HD vectors to identify relevant data.

15. The non-transitory computer readable media of claim 11 , wherein the programmable device pre-defined processing units include hardware components for performing specific tasks in the HD computing machine learning application.

16. The non-transitory computer readable media of claim 11 , where the code generated for the programmable device specifies which resources are to be allocated to each of the pre-defined circuits.

17. The non-transitory computer readable media of claim 11 , wherein the programmable device is configurable for different HD computing machine learning applications by changing the plurality of specifications and parameters for the template architecture.

18. The non-transitory computer readable media of claim 11 , wherein the computer-executable instructions further cause the computing system to:

configure the HD hypervector encoder to map input data features into corresponding hypervectors, wherein encoding is dynamically adjusted based on operational parameters of the HD computing machine learning application, and

configure the HD associative search unit to perform similarity searches within the encoded hypervectors, wherein search operations are prioritized and adjusted based on the real-time resource allocation within the programmable device.