Technologies for preserving error correction capability in compute-in-memory operations

1. A memory device comprising:

a memory controller;

a memory media to store data; and

media access circuitry, separate from the memory controller and local to the memory media, to:

use a reference voltage to read data from the memory media, the reference voltage set in the memory media based on a reference voltage value,

manage an error correction code (ECC) adjustment state to indicate whether errors in the data read from the memory media are any one of correctable and not correctable in the media access circuitry using an ECC, and

perform a compute-in-memory (CIM) operation on the data read from the memory media based on the ECC adjustment state, including to:

determine that the adjustment state is present to pause performance of the CIM operation, and

determine that the adjustment state has been eliminated to resume performance of the CIM operation.

2. A memory device as in claim 1 , wherein to manage the ECC adjustment state, the media access circuitry is to:

attempt to correct, using the ECC, any errors in the data read from the memory media;

for an unsuccessful attempt to correct, set the ECC adjustment state to indicate that the errors are not correctable; and

for a successful attempt to correct, eliminate the ECC adjustment state to indicate that the errors are correctable.

3. A memory device as in claim 2 , wherein errors in the data read from the memory media are:

not correctable for data that exceeds a threshold number of error bits; and

correctable for data that is within the threshold number of error bits.

4. A memory device as in claim 3 wherein, for the unsuccessful attempt to correct, the media access circuitry to manage the ECC adjustment state is further to trigger elimination of the ECC adjustment state using a new reference voltage value.

5. A memory device as in claim 4 , wherein to trigger elimination of the ECC adjustment state using the new reference voltage value, the media access circuitry further to:

determine that a number of error bits in the data read from the memory media exceeds the threshold number of error bits;

determine the new reference voltage value to reduce the number of error bits in the data read from the memory media to within the threshold number of error bits as a function of the reference voltage set by the memory media;

transmit the new reference voltage value to the memory media, the new reference voltage value to cause the memory media to adjust the reference voltage set by the memory media; and

responsive to the memory media having successfully adjusted the reference voltage, eliminate the ECC adjustment state to indicate the errors in the data read from the memory media are correctable.

6. A memory device as in claim 5 , wherein to transmit the new reference voltage value to the memory media, the media access circuitry is to transmit to the memory media any one or more of a signal and a message indicative of the new reference voltage value.

7. A memory device as in claim 1 , wherein the media access circuitry further includes media access circuitry disposed on any of a same die and a same package as the memory media.

8. A memory device as in claim 1 , wherein the media access circuitry further includes media access circuitry disposed on any of a separate die and a separate package from the memory media, including media access circuitry disposed on any of a same dual inline memory module (DIMM) and a same board as the memory media.

9. A system comprising:

a processor;

a memory to store data; and

memory access circuitry, separate from the processor and local to the memory, to:

use a reference voltage to read data from the memory, the reference voltage set by the memory based on a reference voltage value,

manage an error correction code (ECC) adjustment state to indicate whether errors in the data read from the memory are any one of correctable and not correctable in the memory access circuitry using an ECC, and

perform a compute-in-memory (CIM) operation on the data read from the memory based on the ECC adjustment state, including to:

determine that the adjustment state is present to pause performance of the CIM operation, and

determine that the adjustment state has been eliminated to resume performance of the CIM operation.

10. A system as in claim 9 , wherein to manage the ECC adjustment state, the memory access circuitry is to:

attempt to correct, using the ECC, any errors in the data read from the memory;

for an unsuccessful attempt to correct, set the ECC adjustment state to indicate that the errors are not correctable; and

for a successful attempt to correct, eliminate the ECC adjustment state to indicate that the errors are correctable.

11. A system as in claim 10 , wherein errors in the data read from the memory are:

not correctable for data that exceeds a threshold number of error bits; and

correctable for data that is within the threshold number of error bits.

12. A system as in claim 11 , wherein, for the unsuccessful attempt to correct, the memory access circuitry to manage the ECC adjustment state is further to trigger elimination of the ECC adjustment state using a new reference voltage value.

13. A system as in claim 12 , wherein to trigger elimination of the ECC adjustment state using the new reference voltage value, the memory access circuitry further to:

determine that a number of error bits in the data read from the memory exceeds the threshold number of error bits;

determine the new reference voltage value to reduce the number of error bits in the data read from the memory to within the threshold number of error bits as a function of the reference voltage set by the memory;

transmit the new reference voltage value to the memory, the new reference voltage value to cause the memory to adjust the reference voltage set by the memory; and

responsive to the memory having successfully adjusted the reference voltage, eliminate the ECC adjustment state to indicate the errors in the data read from the memory are correctable.

14. A system as in claim 13 , wherein to transmit the new reference voltage value to the memory, the memory access circuitry is to transmit to the memory any one or more of a signal and a message indicative of the new reference voltage value.

15. A system as in claim 9 , wherein the memory access circuitry further includes memory access circuitry disposed on any of a same die and a same package as the memory.

16. A system as in claim 9 , wherein the memory access circuitry further includes memory access circuitry disposed on any of a separate die and a separate package from the memory, including media access circuitry disposed on any of a same dual inline memory module (DIMM) and a same board as the memory.

17. One or more non-transitory machine-readable media comprising a plurality of instructions encoded thereon that, in response to being executed, cause any of a device, system and apparatus having a memory in which to store data, to:

use a reference voltage to read data from the memory, the reference voltage set by the memory based on a reference voltage value;

manage an error correction code (ECC) adjustment state to indicate whether errors in the data read from the memory are any one of correctable and not correctable local to the memory using an ECC; and

perform a compute-in-memory (CIM) operation on the data read from the memory based on the ECC adjustment state, including to:

determine that the adjustment state is present to pause performance of the CIM operation, and

determine that the adjustment state has been eliminated to resume performance of the CIM operation.

18. One or more non-transitory machine-readable media as in claim 17 , wherein to manage the ECC adjustment state, the plurality of instructions encoded thereon is further to cause any of the device, system and apparatus to:

attempt to correct, using the ECC, any errors in the data read from the memory;

for an unsuccessful attempt to correct, set the ECC adjustment state to indicate that the errors are not correctable local to the memory; and

for a successful attempt to correct, eliminate the ECC adjustment state to indicate that the errors are correctable local to the memory.

19. One or more non-transitory machine-readable media as in claim 18 , wherein errors in the data read from the memory are:

not correctable local to the memory for data that exceeds a threshold number of error bits; and

correctable local to the memory for data that is within the threshold number of error bits.

20. One or more non-transitory machine-readable media as in claim 19 , wherein, for the unsuccessful attempt to correct, the plurality of instructions to manage the ECC adjustment state is further to cause any of the device, system and apparatus to trigger elimination of the ECC adjustment state using a new reference voltage value.

21. One or more non-transitory machine-readable media as in claim 20 , wherein to trigger elimination of the ECC adjustment state using the new reference voltage value, the plurality of instructions is further to cause any of the device, system and apparatus to:

determine that a number of error bits in the data read from the memory exceeds the threshold number of error bits;

determine the new reference voltage value to reduce the number of error bits to within the threshold number of error bits as a function of the reference voltage set by the memory;

transmit the new reference voltage value to the memory, the new reference voltage value to cause the memory to adjust the reference voltage set by the memory; and

responsive to the memory having successfully adjusted the reference voltage, eliminate the ECC adjustment state to indicate the errors in the data read from the memory are correctable.

22. One or more non-transitory machine-readable media as in claim 21 , wherein to transmit the new reference voltage value to the memory, the plurality of instructions is further to cause any of the device, system and apparatus to transmit to the memory any one or more of a signal and a message indicative of the new reference voltage value.

23. One or more non-transitory machine-readable media as in claim 17 , wherein the plurality of instructions encoded thereon are implemented in any of a same die and a same package as the memory.

24. One or more non-transitory machine-readable media as in claim 17 , wherein the plurality of instructions encoded thereon are implemented in any of a separate die and a separate package from the memory, including any of a same dual inline memory module (DIMM) and a same board as the memory.