Low-noise high efficiency bias generation circuits and method
An apparatus for generating a steady state positive voltage (PVS) signal and a steady state negative voltage (NVS) signal is presented. The apparatus includes a bias signal generation module for generating a steady state reference voltage signal (RVS) based on a varying supply voltage signal (VDD), the RVS having a voltage level less than the PVS. The apparatus further includes a positive signal generation module (PSGM) generating the PVS, the PSGM including a first capacitor, the PSGM employing the first capacitor to generate a portion of the PVS based on the RVS. The apparatus further includes a negative signal generation module (NSGM) generating the NVS, the NSGM including a second capacitor, the NSGM employing the second capacitor to generate a portion of the NVS based on the RVS.
1. An apparatus for generating a substantially stable positive voltage signal (PVS), comprising:
a bias signal generation module (BSGM) for generating a stable reference voltage signal (RVS) based on a varying supply voltage signal (VDD), the RVS having a voltage level that is less than a voltage level of the PVS;
a positive voltage charge pump module (PVCPM) for generating the PVS, the PVCPM including a first charge pump capacitor, the PVCPM employing the first charge pump capacitor to generate a portion of the PVS based on the RVS; and
at least one radio frequency (RF) switch coupled to the PVCPM for receiving the PVS,
wherein the PVS is configured to remain substantially stable during a switching event of said RF switch.
2. The apparatus of claim 1 , wherein:
the BSGM comprises a bandgap reference module (BRM) for generating the RVS based on a regulated version of the VDD.
3. The apparatus of claim 1 , wherein:
the PVCPM is a voltage level increase charge pump.
4. The apparatus of claim 1 , further comprising:
a voltage regulator for generating a positive charge pump input voltage (POS_CP_IN) to the PVPCM based on the RVS.
5. The apparatus of claim 4 , wherein:
the voltage regulator is a low dropout (LDO) voltage regulator.
6. The apparatus of claim 4 , wherein:
a voltage level of the POS_CP_IN is greater than the voltage level of the RVS.
7. The apparatus of claim 4 , wherein:
a voltage level of the POS_CP_IN is about half the voltage level of the PVS.
8. The apparatus of claim 4 , wherein:
the first charge pump capacitor is part of a charge pump circuit that steps up a volage level of the POS_CP_IN to the voltage level of the PVS.
9. The apparatus of claim 4 , further comprising:
an amplifier for generating a difference between the RVS and a voltage based on the PVS, the difference used for generating the POS_CP_IN.
10. The apparatus of claim 9 , wherein:
the voltage based on the PVS, is a divided version of the PVS.
11. The apparatus of claim 10 , wherein:
the divided version of the PVS is provided by a voltage divider comprising a plurality of resistors.
12. The apparatus of claim 9 , wherein:
the difference is used as input to the voltage regulator.
13. The apparatus of claim 4 , further comprising:
an oscillator for providing at least one clock signal to the PVCPM.
14. The apparatus of claim 13 , wherein:
the oscillator further provides an additional clock signal to the PVCPM, the at least one clock signal and the additional clock signal being differential clock signals.
15. The apparatus of claim 14 , wherein:
the differential clock signals alternatively charge and discharge the first charge pump capacitor to generate the portion of the PVS.
16. The apparatus of claim 15 , wherein during a discharging phase of the first charge pump capacitor:
a bottom plate of said capacitor is at a voltage level of the POS_CP_IN, and
a top plate of said capacitor is at a voltage level that is about twice the voltage level at the bottom plate.
17. The apparatus of claim 15 , wherein:
the PVCPM further employs a second charge pump capacitor to generate another portion of the PVS based on the RVS.
18. The apparatus of claim 17 , wherein:
the first and second charge pump capacitors are part of a charge pump circuit that steps up a volage level of the POS_CP_IN to the voltage level of the PVS.
19. The apparatus of claim 1 , further comprising:
a negative signal generation module (NSGM) for generating a stable negative voltage signal (NVS), the NSGM including a respective charge pump capacitor, the NSGM employing the respective charge pump capacitor to generate a portion of the NVS based on the RVS;
wherein the at least one RF switch is further coupled to the NSGM for receiving the NVS, and
wherein the NVS is configured to remain substantially stable during a switching event of said RF switch.
20. An apparatus for generating a substantially stable positive voltage signal (PVS), comprising:
a bandgap reference module (BRM) for generating a stable reference voltage signal (RVS) based on a varying supply voltage signal (VDD), the RVS having a voltage level that is less than a voltage level of the PVS;
a positive charge pump module (PCPM) for generating the PVS, the PCPM including a first charge pump capacitor;
an amplifier for generating a difference between the RVS and a voltage based on the PVS; and
a voltage regulator employing the difference for generating a positive charge pump input voltage (POS_CP_IN) to the PCPM;
wherein the PCPM employs the first charge pump capacitor to generate a portion of the PVS based on the POS_CP_IN, and
wherein the PVS is configured to remain substantially stable during a switching event of an RF switch coupled to the PVS.
21. The apparatus of claim 20 , further comprising:
an oscillator for providing at least one clock signal to the PVCPM.
22. The apparatus of claim 21 , wherein:
the oscillator further provides an additional clock signal to the PVCPM, the at least one clock signal and the additional clock signal being differential clock signals.
23. The apparatus of claim 22 , wherein:
the differential clock signals alternatively charge and discharge the first charge pump capacitor to generate the portion of the PVS.
24. The apparatus of claim 23 , wherein during a discharging phase of the first charge pump capacitor:
a bottom plate of said capacitor is at a voltage level of the POS_CP_IN, and
a top plate of said capacitor is at a voltage level that is about twice the voltage level at the bottom plate.
25. The apparatus of claim 23 , wherein:
the PCPM further employs a second charge pump capacitor to generate another portion of the PVS based on the RVS.
26. A method for generating a substantially stable positive voltage signal (PVS), comprising:
generating, via a bandgap reference module (BRM), a stable reference voltage signal (RVS) based on a varying supply voltage signal (VDD), the RVS having a voltage level that is less than a voltage level of the PVS;
generating, via a positive charge pump module (PCPM), the PVS, the PCPM including a first charge pump capacitor;
generating, via an amplifier, a difference between the RVS and a voltage based on the PVS; and
generating, by inputting the difference to a voltage regulator, a positive charge pump input voltage (POS_CP_IN) to the PCPM;
wherein the PCPM employs the first charge pump capacitor to generate a portion of the PVS based on the POS_CP_IN, and
wherein the PVS is configured to remain substantially stable during a switching event of an RF switch coupled to the PVS.