Disaggregated computing for distributed confidential computing environment
An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a processor executing a trusted execution environment (TEE) comprising a field-programmable gate array (FPGA) driver to interface with an FPGA device that is remote to the apparatus; and a remote memory-mapped input/output (MMIO) driver to expose the FPGA device as a legacy device to the FPGA driver, wherein the processor to utilize the remote MMIO driver to: enumerate the FPGA device using FPGA enumeration data provided by a remote management controller of the FPGA device, the FPGA enumeration data comprising a configuration space and device details; load function drivers for the FPGA device in the TEE; create corresponding device files in the TEE based on the FPGA enumeration data; and handle remote MMIO reads and writes to the FPGA device via a network transport protocol.
1. An apparatus comprising:
a processor executing a trusted execution environment (TEE) comprising a field-programmable gate array (FPGA) driver to interface with an FPGA device that is remote to the apparatus; and a remote memory-mapped input/output (MMIO) driver to expose the FPGA device as a legacy device to the FPGA driver, wherein the processor to utilize the remote MMIO driver to:
enumerate the FPGA device using FPGA enumeration data provided by a remote management controller of the FPGA device, the FPGA enumeration data comprising a configuration space and device details;
load function drivers for the FPGA device in the TEE;
create corresponding device files in the TEE based on the FPGA enumeration data; and
handle remote MMIO reads and writes to the FPGA device via a network transport protocol.
2. The apparatus of claim 1 , wherein the legacy device comprises a peripheral component interconnect express (PCIe) device.
3. The apparatus of claim 1 , wherein the FPGA enumeration data comprises a size of a base address register (BAR) regions utilized by the FPGA device.
4. The apparatus of claim 3 , wherein the remote MMIO driver is to create the corresponding device files representing the BAR regions of the FPGA device.
5. The apparatus of claim 1 , wherein the processor to utilize the remote MMIO driver to handle remote MMIO reads and writes further comprises the processor to:
convert a MMIO request received from a host driver of the TEE into a remote MMIO request, the MMIO request comprising at least one of the remote MMIO reads and writes;
packetize the remote MMIO request as a packetized remote MMIO request; and
send the packetized remote MMIO request to the FPGA device directly via the network transport protocol.
6. The apparatus of claim 1 , wherein the network transport protocol comprises remote direct memory access (RDMA).
7. The apparatus of claim 5 , wherein the remote management controller of the FPGA is to:
receive the packetized remote MMIO request;
parse the packetized remote MMIO request;
perform a corresponding memory read or write to registers of the FPGA device; and
return a status message indicating success or failure of the corresponding memory write or indicating a read response.
8. The apparatus of claim 1 , wherein the remote management controller comprises a message parser to initiate memory read and write requests to the FPGA device and a buffer for storing messages.
9. A method comprising:
enumerating, by a processor utilizing a remote memory-mapped input/output (MMIO) driver of a trusted execution environment (TEE), a field-programmable gate array (FPGA) device using FPGA enumeration data provided by a remote management controller of the FPGA device, the FPGA enumeration data comprising a configuration space and device details;
loading, by the processor utilizing the remote MMIO driver, function drivers for the FPGA device in the TEE and create corresponding device files in the TEE based on the FPGA enumeration data; and
handling, by the processor utilizing the remote MMIO driver, remote MMIO reads and writes to the FPGA device via a network transport protocol, wherein an FPGA driver to interface with an FPGA device.
10. The method of claim 9 , wherein the MMIO driver to expose the FPGA device as a legacy device to the FPGA driver, and wherein the legacy device comprises a peripheral component interconnect express (PCIe) device.
11. The method of claim 9 , wherein the FPGA enumeration data comprises a size of a base address register (BAR) regions utilized by the FPGA device.
12. The method of claim 9 , wherein handling the remote MMIO reads and writes further comprises:
converting a MMIO request received from a host driver of the TEE into a remote MMIO request, the MMIO request comprising at least one of the remote MMIO reads and writes;
packetizing the remote MMIO request as a packetized remote MMIO request; and
sending the packetized remote MMIO request to the FPGA device directly via the network transport protocol.
13. The method of claim 9 , wherein the network transport protocol comprises remote direct memory access (RDMA).
14. The method of claim 12 , wherein the remote management controller of the FPGA is to:
receive the packetized remote MMIO request;
parse the packetized remote MMIO request;
perform a corresponding memory read or write to registers of the FPGA device; and
return a status message indicating success or failure of the corresponding memory write or indicating a read response.
15. The method of claim 9 , wherein the remote management controller comprises a message parser to initiate memory read and write requests to the FPGA device and a buffer for storing messages.
16. A non-transitory machine readable storage medium having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations to:
enumerating, by the one or more processors utilizing a remote memory-mapped input/output (MMIO) driver of a trusted execution environment (TEE) comprising at least one processor of the one or more processors, a field-programmable gate array (FPGA) device using FPGA enumeration data provided by a remote management controller of the FPGA device, the FPGA enumeration data comprising a configuration space and device details;
loading, by the remote MMIO driver, function drivers for the FPGA device in the TEE and create corresponding device files in the TEE based on the FPGA enumeration data; and
handling, by the remote MMIO driver, remote MMIO reads and writes to the FPGA device via a network transport protocol, wherein an FPGA driver to interface with an FPGA device.
17. The non-transitory machine readable storage medium of claim 16 , wherein the FPGA enumeration data comprises a size of a base address register (BAR) regions utilized by the FPGA device.
18. The non-transitory machine readable storage medium of claim 17 , wherein the remote MMIO driver creates the corresponding device files representing the BAR regions of the FPGA device.
19. The non-transitory machine readable storage medium of claim 16 , wherein the remote MMIO driver to handle remote MMIO reads and writes further comprises:
converting a MMIO request received from a host driver of the TEE into a remote MMIO request, the MMIO request comprising at least one of the remote MMIO reads and writes;
packetizing the remote MMIO request as a packetized remote MMIO request; and
sending the packetized remote MMIO request to the FPGA device directly via the network transport protocol.
20. The non-transitory machine readable storage medium of claim 19 , wherein the remote management controller of the FPGA is to:
receive the packetized remote MMIO request;
parse the packetized remote MMIO request;
perform a corresponding memory read or write to registers of the FPGA device; and
return a status message indicating success or failure of the corresponding memory write or indicating a read response.