Disaggregated computing for distributed confidential computing environment
An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.
1. An apparatus comprising:
a processor executing a secure environment comprising a field-programmable gate array (FPGA) driver to interface with an FPGA device that is remote to the apparatus, wherein the processor is to:
enumerate the FPGA device using FPGA enumeration data provided by a remote management controller of the FPGA device, the FPGA enumeration data comprising a configuration space and device details;
load function drivers for the FPGA device in the secure environment;
create corresponding device files in the secure environment based on the FPGA enumeration data; and
handle remote reads and remote writes to the FPGA device via a network transport protocol.
2. The apparatus of claim 1 , wherein the secure environment comprises a trusted execution environment (TEE).
3. The apparatus of claim 1 , wherein the FPGA enumeration data comprises a size of a base address register (BAR) regions utilized by the FPGA device.
4. The apparatus of claim 3 , wherein the processor is further to create the corresponding device files representing the BAR regions of the FPGA device.
5. The apparatus of claim 1 , wherein the processor to handle the remote reads and the remote writes further comprises the processor to:
convert a memory-mapped input/output (MMIO) request received from a host driver of the secure environment into a remote MMIO request, the remote MMIO request comprising at least one of the remote reads or the remote writes;
packetize the remote MMIO request into a packetized remote MMIO request; and
send the packetized remote MMIO request to the FPGA device directly via the network transport protocol.
6. The apparatus of claim 1 , wherein the network transport protocol comprises remote direct memory access (RDMA).
7. The apparatus of claim 5 , wherein the remote management controller of the FPGA device is to:
receive the packetized remote MMIO request;
parse the packetized remote MMIO request;
perform a corresponding memory read or a corresponding memory write to registers of the FPGA device; and
return a status message indicating success or failure of the corresponding memory write or indicating a read response.
8. The apparatus of claim 1 , wherein the remote management controller comprises a message parser to initiate memory read and write requests to the FPGA device and a buffer for storing messages.
9. A method comprising:
enumerating, by a processor a field-programmable gate array (FPGA) device using FPGA enumeration data provided by a remote management controller of the FPGA device, the FPGA enumeration data comprising a configuration space and device details;
loading, by the processor, function drivers for the FPGA device in a secure environment of the processor and create corresponding device files in the secure environment based on the FPGA enumeration data; and
handling, by the processor, remote reads and remote writes to the FPGA device via a network transport protocol, wherein an FPGA driver to interface with an FPGA device.
10. The method of claim 9 , wherein the secure environment comprises a trusted execution environment (TEE).
11. The method of claim 9 , wherein the FPGA enumeration data comprises a size of a base address register (BAR) regions utilized by the FPGA device.
12. The method of claim 9 , wherein handling the remote reads and the remote writes further comprises:
converting a memory-mapped input/output (MMIO) request received from a host driver of the secure environment into a remote MMIO request, the remote MMIO request comprising at least one of the remote reads or the remote writes;
packetizing the remote MMIO request into a packetized remote MMIO request; and
sending the packetized remote MMIO request to the FPGA device directly via the network transport protocol.
13. The method of claim 9 , wherein the network transport protocol comprises remote direct memory access (RDMA).
14. The method of claim 12 , wherein the remote management controller of the FPGA device is to:
receive the packetized remote MMIO request;
parse the packetized remote MMIO request;
perform a corresponding memory read or a corresponding memory write to registers of the FPGA device; and
return a status message indicating success or failure of the corresponding memory write or indicating a read response.
15. The method of claim 9 , wherein the remote management controller comprises a message parser to initiate memory read and write requests to the FPGA device and a buffer for storing messages.
16. A non-transitory machine readable storage medium having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations to:
enumerating, by the one or more processors a field-programmable gate array (FPGA) device using FPGA enumeration data provided by a remote management controller of the FPGA device, the FPGA enumeration data comprising a configuration space and device details;
loading function drivers for the FPGA device in a secure environment of the one or more processors and create corresponding device files in the secure environment based on the FPGA enumeration data; and
handling remote reads and remote writes to the FPGA device via a network transport protocol, wherein an FPGA driver to interface with an FPGA device.
17. The non-transitory machine readable storage medium of claim 16 , wherein the FPGA enumeration data comprises a size of a base address register (BAR) regions utilized by the FPGA device.
18. The non-transitory machine readable storage medium of claim 17 , wherein the operations further comprise creating the corresponding device files representing the BAR regions of the FPGA device.
19. The non-transitory machine readable storage medium of claim 16 , wherein handling the remote reads and the remote writes further comprises:
converting memory-mapped input/output (MMIO) request received from a host driver of the secure environment into a remote MMIO request, the remote MMIO request comprising at least one of the remote reads or the remote writes;
packetizing the remote MMIO request into a packetized remote MMIO request; and
sending the packetized remote MMIO request to the FPGA device directly via the network transport protocol.
20. The non-transitory machine readable storage medium of claim 19 , wherein the remote management controller of the FPGA device is to:
receive the packetized remote MMIO request;
parse the packetized remote MMIO request;
perform a corresponding memory read or a corresponding memory write to registers of the FPGA device; and
return a status message indicating success or failure of the corresponding memory write or indicating a read response.