Carrier based high volume system level testing of devices with pop structures
A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.
1. A testing apparatus comprising:
a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises:
an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket of the plurality of sockets operable to receive a device under test (DUT);
a carrier comprising an array of DUTs, wherein the carrier is operable to position into the slot of the rack, and wherein each DUT in the array of DUTs aligns with a respective socket of the plurality of sockets on the interface board and wherein the carrier is a discrete component separate from the interface board and the plurality of sockets; and
an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs;
a pick-and-place mechanism for loading the array of DUTs into the carrier; and
an elevator for transporting the carrier to the slot of the rack.
2. The testing apparatus of claim 1 , wherein the plurality of slots are vertically oriented.
3. The testing apparatus of claim 1 , wherein the plurality of slots are horizontally oriented.
4. The testing apparatus of claim 1 , wherein the array of POP memory devices is placed into position using a parallel cover assembly system.
5. The testing apparatus of claim 1 , wherein each slot further comprises an array of actuators, wherein each actuator of the array of actuators is operable to actuate a socket cover above each POP memory device and corresponding DUT to bring the POP memory device and the corresponding DUT in contact with a respective socket of the plurality of sockets.
6. The testing apparatus of claim 1 , wherein a first subset of the plurality of slots are horizontally oriented and a second subset of the plurality of slots different from the first subset of the plurality of slots are vertically oriented.
7. The testing apparatus of claim 1 , wherein each DUT of the array of DUTs comprises pads on a top surface where a respective POP memory device can make contact.
8. The testing apparatus of claim 1 , wherein each DUT of the array of DUTs is an application processor and each respective POP memory device comprises memory operable to performing a system level test of the application processor in conjunction with the memory.
9. The testing apparatus of claim 1 , wherein the elevator comprises a dual-slot elevator, wherein the dual-slot elevator further comprises two slots, wherein a first slot is operable to transport the carrier to the slot of the rack, and wherein a second slot is operable to transport a transport a different carrier previously loaded into the slot of the rack.
10. A testing system comprising:
a station operable to load and unload devices under test (DUTs) from a plurality of carriers, wherein the station comprises a pick-and-place mechanism and a trolley operable to transport the plurality of carriers between the station and at least one tester;
the at least one tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises:
an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT);
a carrier comprising an array of DUTs, wherein the carrier is operable to position into the slot of the rack, and wherein each DUT in the array of DUTs aligns with a respective socket of the plurality of sockets on the interface board and wherein the carrier is a discrete component separate from the interface board and the plurality of sockets; and
an array of POP memory nests, wherein each POP memory nest comprises a POP memory device and is disposed adjacent to respective DUT in the array of DUTs;
an elevator for transporting the carrier to the slot of the rack from the trolley.
11. The testing system of claim 10 , wherein each DUT of the array of DUTs comprises pads on a top surface where a respective POP memory device can make contact.
12. The testing system of claim 10 , wherein each POP memory nest is associated with a floating nest operable to adjust in an X-Y direction in order to align the POP memory nest with pads on a surface of a corresponding DUT.
13. The testing system of claim 10 , wherein the plurality of slots associated with the at least one tester are vertically oriented.
14. The testing system of claim 10 , wherein the plurality of slots associated with the at least one tester are horizontally oriented.
15. The testing system of claim 10 , wherein each DUT of the array of DUTs is an application processor and each respective POP memory nest of the array of POP memory nests comprises a memory device operable to performing a system level test of the application processor in conjunction with the memory device.