Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same
Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same are described. An example semiconductor-superconductor hybrid device includes a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate, having a first top surface, formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate, having a second top surface, formed adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, where each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a selected surface of the semiconductor heterostructure by a predetermined offset amount.
1 . A semiconductor-superconductor hybrid device comprising:
a semiconductor heterostructure formed over a substrate;
a superconducting layer formed over the semiconductor heterostructure;
a first gate, having a first top surface, formed adjacent to a first side of the semiconductor heterostructure; and
a second gate, having a second top surface, formed adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, wherein each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a top surface of the semiconductor heterostructure by a predetermined offset amount, wherein the semiconductor-superconductor hybrid device is configured to form a horizontally-confined electrostatic channel in the semiconductor heterostructure in response to an application of an electric field to the semiconductor heterostructure via the first gate and the second gate, wherein the predetermined offset amount is selected to ensure that the horizontally-confined electrostatic channel is formed at a selected distance from the top surface of the semiconductor heterostructure to reduce an effect of any structural disorder associated with an interface of the superconducting layer with the semiconductor heterostructure, and wherein the structural disorder associated with the interface comprises line edge roughness (LER) associated with the superconducting layer.
2 . The semiconductor-superconductor hybrid device of claim 1 , wherein the horizontally-confined electrostatic channel comprises one of a 2-dimensional electron gas (2-DEG) channel or a 2-dimensional hole gas (2-DHG) channel.
3 . The semiconductor-superconductor hybrid device of claim 1 , further comprising a first terminal coupled to the first gate and a second terminal coupled to the second gate, wherein the electric field is generated by an application of a first voltage to the first terminal and a second voltage to the second terminal.
4 . The semiconductor-superconductor hybrid device of claim 3 , wherein an amount of the first voltage and an amount of the second voltage is selected to tune a width associated with the horizontally-confined electrostatic channel.
5 . The semiconductor-superconductor hybrid device of claim 1 , wherein the semiconductor-superconductor hybrid device is operable as a nanowire having a tunable width.
6 . The semiconductor-superconductor hybrid device of claim 1 , wherein the predetermined offset is determined by testing samples of multiple devices to increase a mobility of electrons within the horizontally-confined electrostatic channel.
7 . The semiconductor-superconductor hybrid device of claim 1 , wherein the predetermined offset is determined by testing samples of multiple devices to increase a density of electrons within the horizontally-confined electrostatic channel.
8 . An integrated circuit including a semiconductor-superconductor hybrid device comprising:
a semiconductor heterostructure formed over a substrate;
a superconducting layer formed over the semiconductor heterostructure;
a first gate, having a first top surface, formed adjacent to a first side of the semiconductor heterostructure; and
a second gate, having a second top surface, formed adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, wherein each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a top surface of the semiconductor heterostructure by a predetermined offset amount, wherein the predetermined offset amount is selected to ensure that a horizontally-confined electrostatic channel is formed at a selected distance from the top surface of the semiconductor heterostructure to reduce an effect of any structural disorder associated with an interface of the superconducting layer with the semiconductor heterostructure, and wherein the structural disorder associated with the interface comprises line edge roughness (LER) associated with the superconducting layer; and
wherein the integrated circuit further comprises a controller coupled with the semiconductor-superconductor hybrid device, wherein the horizontally-confined electrostatic channel is formed in response to an electric field generated by an application of a first voltage to a first terminal associated with the first gate and a second voltage to a second terminal associated with the second gate, and wherein the first voltage and the second voltage is generated using at least one voltage regulator included within the controller coupled with the semiconductor-superconductor hybrid device.
9 . The integrated circuit of claim 5 , wherein the horizontally-confined electrostatic channel in the semiconductor heterostructure is formed in response to an application of an electric field to the semiconductor heterostructure via the first gate and the second gate.
10 . The integrated circuit of claim 5 , wherein the horizontally-confined electrostatic channel comprises one of a 2-dimensional electron gas (2-DEG) channel or a 2-dimensional hole gas (2-DHG) channel.
11 . The integrated circuit of claim 8 , wherein an amount of the first voltage and an amount of the second voltage is selected to tune a width associated with the horizontally-confined electrostatic channel.
12 . The integrated circuit of claim 8 , wherein the semiconductor-superconductor hybrid device is operable as a nanowire having a tunable width.
13 . A semiconductor-superconductor hybrid device comprising:
a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure formed over a substrate;
a left gate formed adjacent to a first side of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure;
a right gate formed adjacent to a second side, opposite to the first side, of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure, wherein a top surface of each of the left gate and the right gate is offset vertically from a top surface of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure by a predetermined offset amount, wherein the semiconductor-superconductor hybrid device is configured to form a horizontally-confined electrostatic channel in a respective isolated semiconductor heterostructure in response to an application of an electric field to the respective isolated semiconductor heterostructure via a respective left gate and a respective right gate, wherein the predetermined offset amount is selected to ensure that the horizontally-confined electrostatic channel is formed at a selected distance from the top surface of the respective isolated semiconductor heterostructure to reduce an effect of any structural disorder associated with an interface of the superconducting layer with the respective isolated semiconductor heterostructure, and wherein the structural disorder associated with the interface comprises line edge roughness (LER) associated with the superconducting layer; and
a superconducting layer formed over each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure.
14 . The semiconductor-superconductor hybrid device of claim 13 , further comprising a first terminal coupled to the first gate and a second terminal coupled to the second gate, wherein the electric field is generated by an application of a first voltage to the first terminal and a second voltage to the second terminal.
15 . The semiconductor-superconductor hybrid device of claim 14 , wherein an amount of the first voltage and an amount of the second voltage is selected to tune a width associated with the horizontally-confined electrostatic channel.
16 . The semiconductor-superconductor hybrid device of claim 13 , wherein the horizontally-confined electrostatic channel comprises one of a 2-dimensional electron gas (2-DEG) channel or a 2-dimensional hole gas (2-DHG) channel.
17 . The semiconductor-superconductor hybrid device of claim 13 , wherein the semiconductor-superconductor hybrid device is operable as a nanowire having a tunable width.
18 . The semiconductor-superconductor hybrid device of claim 13 , wherein the predetermined offset is determined by testing samples of multiple devices to increase a mobility of electrons within the horizontally-confined electrostatic channel.
19 . The semiconductor-superconductor hybrid device of claim 13 , wherein the predetermined offset is determined by testing samples of multiple devices to increase a density of electrons within the horizontally-confined electrostatic channel.