Side-gating in selective-area-grown topological qubits
A quantum device is fabricated by forming a network of nanowires oriented in a plane of a substrate to produce a Majorana-based topological qubit. The nanowires are formed from combinations of selective-area-grown semiconductor material along with regions of a superconducting material. The selective-area-grown semiconductor material is grown by etching trenches to define the nanowires and depositing the semiconductor material in the trenches. A side gate is formed in an etched trench and situated to control a topological segment of the qubit.
1. A method for fabricating a quantum device, the method comprising:
providing a substrate and an insulator formed on the substrate;
from combinations of selective-area-grown semiconductor material along with regions of a superconducting material, forming a network of nanowires oriented in a plane of the substrate that is gateable to produce a Majorana-based topological qubit; and
fabricating a side gate for controlling a topological segment of the Majorana-based topological qubit;
wherein the selective-area-grown semiconductor material is grown on the substrate by etching trenches in the insulator formed on the substrate to define the nanowires and depositing the semiconductor material in the trenches defining the nanowires; and
wherein the fabricating of the side gate comprises etching the insulator to create a trench for the side gate and depositing the side gate in the trench for the side gate.
2. The method of claim 1 , wherein the side gate is fabricated from one of the regions of selective area grown semiconductor.
3. The method of claim 2 , wherein the side gate is formed in the same fabrication steps as the network of nanowires.
4. The method of claim 1 , wherein the regions of superconducting material include regions coated on the semiconductor material that is deposited in the trenches defining the nanowires.
5. The method of claim 1 , wherein the regions of superconductor are deposited simultaneously using a mechanical mask.
6. The method of claim 1 , wherein the insulator formed on the substrate is a dielectric.
7. The method of claim 1 , further comprising covering the insulator formed on the substrate and the side gates with a further, protective insulating layer.
8. The method of claim 1 , wherein the substrate is an insulating material.
9. The method of claim 1 , wherein the regions of superconducting material form superconducting islands, some parts of which are topological and some parts of which are non-topological; said topological segment being one of said topological parts.
10. The method of claim 9 , wherein the non-topological parts are s-wave superconductors; and wherein Majorana zero modes appear in pairs at ends of linear parts of the topological segments, and where the qubit comes into contact with either an s-wave superconductor or an insulator.
11. The method of claim 1 , wherein the etching is by lithography.
12. The method of claim 1 , wherein the growth of the semiconductor material and/or the depositing of the side gate is by epitaxy.
13. The method of claim 1 , wherein:
the Majorana-based topological qubit is a quad qubit, and the side gate is configured to tune the Fermi energy of the topological segment; or
the Majorana-based topological qubit is a hexon qubit, and the side gate is configured to tune the Fermi energy of one or more topological segments in the network of nanowires.
14. A method of operating a quantum device fabricated according to the method of claim 1 , wherein:
the topological segment of the qubit is a topologically protected segment and the side gate is located adjacent to the topologically protected segment; and
the method of operating the quantum device comprises electrically controlling the side gate, and thereby creating a state in the topologically protected segment comprising a Majorana zero mode pair.
15. A quantum device comprising:
a substrate and an insulator formed on the substrate;
combinations of selective-area-grown semiconductor material along with regions of a superconducting material, forming a network of nanowires oriented in the plane of the substrate that is gateable to produce a Majorana-based topological qubit; and
a side gate for controlling a topological segment of the Majorana-based topological qubit;
wherein the selective-area-grown semiconductor material is buried in trenches in the insulator which define the nanowires, and wherein side gate is also buried in a trench in the insulator.