IP Library › Granted Patent US 12,272,746
Granted Patent B2
US 12,272,746 · App. 17/533,843 · Granted Apr 8, 2025

Semiconductor device

Inventor: Keiji Okumura (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/7811H01L29/66068H01L29/66734H01L29/1608H01L29/2003H01L29/66522H01L29/7813
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Quick Facts
Patent No.
US 12,272,746
App. No.
17/533,843
Granted
Apr 8, 2025
Kind
B2
Abstract

A semiconductor device has an active area in which a main current flows and an outer-edge area surrounding the active area. The semiconductor device includes: an n-type semiconductor layer made of a wide bandgap semiconductor; a plurality of p-type guard rings provided inside the semiconductor layer in the outer-edge area to surround the active area; and a separation region provided in a concentric ring shape in the outer-edge area to be in contact with both of the adjacent guard rings, wherein the separation region contains both n-type first impurities and p-type second impurities.

Claims (53)

1. A semiconductor device having an active area in which a main current flows and an outer-edge area surrounding the active area, the semiconductor device comprising:

a semiconductor layer having a first conductivity type made of a wide bandgap semiconductor;

a plurality of guard rings each having a second conductivity type provided inside the semiconductor layer in the outer-edge area to surround the active area; and

a separation region provided in a concentric ring shape in the outer-edge area to be in contact with adjacent guard rings among the plurality of guard rings inside the semiconductor layer whereby the adjacent guard rings are separated from each other by the separation region,

wherein the separation region contains both first impurities of the first conductivity type and second impurities of the second conductivity type,

wherein a top surface of the semiconductor layer has an offset angle in a range of greater than 0° and equal to or less than about 10° in a <11-20> direction with respect to a <0001> direction.

2. The semiconductor device of claim 1 , wherein the separation region is a semiconductor region of the first conductivity type.

3. The semiconductor device of claim 1 , wherein the separation region is a semiconductor region of the second conductivity type.

4. The semiconductor device of claim 1 , wherein a mesa groove is provided in the outer-edge area.

5. The semiconductor device of claim 1 , wherein the wide bandgap semiconductor is any one of silicon carbide, gallium nitride, and aluminum nitride.

6. A semiconductor device having an active area in which a main current flows and an outer-edge area surrounding the active area, the semiconductor device comprising:

a semiconductor layer having a first conductivity type made of a wide bandgap semiconductor;

a plurality of guard rings each having a second conductivity type provided inside the semiconductor layer in the outer-edge area to surround the active area; and

a separation region provided in a concentric ring shape in the outer-edge area to be in contact with both of adjacent guard rings, wherein the separation region contains both first impurities of the first conductivity type and second impurities of the second conductivity type,

wherein, in a depth where the guard rings and the separation region are in contact with each other, an impurity concentration of the second impurity in the separation region is the same as an impurity concentration of impurities of the second conductivity type contained in each of the guard rings.

7. A semiconductor device having an active area in which a main current flows and an outer-edge area surrounding the active area, the semiconductor device comprising:

a semiconductor layer having a first conductivity type made of a wide bandgap semiconductor;

a plurality of guard rings each having a second conductivity type provided inside the semiconductor layer in the outer-edge area to surround the active area; and

a separation region provided in a concentric ring shape in the outer-edge area to be in contact with adjacent guard rings among the plurality of guard rings inside the semiconductor layer whereby the adjacent guard rings are separated from each other by the separation region,

wherein the separation region contains both first impurities of the first conductivity type and second impurities of the second conductivity type,

wherein the active area including:

a base region of the second conductivity type provided on a top surface of the semiconductor layer;

a source region of the first conductivity type selectively provided on an upper portion of the base region;

a base contact region of the second conductivity type selectively provided on an upper portion of the base region;

a trench which penetrates the base region to reach the semiconductor layer,

an insulated-gate electrode structure provided inside the trench;

a gate-bottom protection region of the second conductivity type provided to be in contact with a bottom of the trench; and

a base-bottom embedded region of the second conductivity type provided inside the semiconductor layer to be in contact with a bottom surface of the base region.

8. The semiconductor device of claim 7 , wherein an impurity concentration of second conductivity type impurities contained in each of the guard rings is the same as an impurity concentration of second conductivity type impurities contained in the base region.

9. The semiconductor device of claim 7 , wherein each depth of the guard rings is the same as a depth of the base contact region, and a depth of the separation region is the same as a depth of the source region.

10. The semiconductor device of claim 7 , wherein an impurity concentration of second conductivity type impurities contained in each of the guard rings is the same as an impurity concentration of second conductivity type impurities contained in the base contact region, and an impurity concentration of the first impurities of the first conductivity type contained in the separation region is the same as an impurity concentration of first conductivity type impurities contained in the source region.

11. A semiconductor device having an active area in which a main current flows and an outer-edge area surrounding the active area, the semiconductor device comprising:

a semiconductor layer having a first conductivity type made of a wide bandgap semiconductor;

a plurality of guard rings each having a second conductivity type provided inside the semiconductor layer in the outer-edge area to surround the active area; and

a separation region provided in a concentric ring shape in the outer-edge area to be in contact with adjacent guard rings among the plurality of guard rings inside the semiconductor layer whereby the adjacent guard rings are separated from each other by the separation region,

wherein the separation region contains both first impurities of the first conductivity type and second impurities of the second conductivity type,

wherein each of the guard rings has a first region and a second region in contact with a bottom surface of the first region, the second region having a width different from that of the first region.

12. A method for manufacturing a semiconductor device having an active area in which a main current flows and an outer-edge area surrounding the active area in a first conductivity type semiconductor layer made of a wide bandgap semiconductor, the method including:

forming a second conductivity type semiconductor region on a top surface of the semiconductor layer from the active area to the outer-edge area; and

forming separation regions by implanting first conductivity type impurity ions into the semiconductor region to reach the semiconductor layer, the separation regions each having a concentric ring shape and guard rings sandwiching between the respective separation regions in the outer-edge area.

13. The method of claim 12 , wherein, the separation regions are formed in a depth where the guard rings and the separation regions are in contact with each other, so that an impurity concentration of the second impurity in each of the separation regions is the same as an impurity concentration of impurities of the second conductivity type contained in each of the guard rings.

14. The method of claim 12 , further executed in the active area, the method including:

forming a base region of the second conductivity type on a top surface of the semiconductor layer;

selectively forming a source region of the first conductivity type on an upper portion of the base region;

selectively forming a base contact region of the second conductivity type on the upper portion of the base region;

forming a trench which penetrates the base region to reach the semiconductor layer;

forming an insulated-gate electrode structure inside the trench;

forming a gate-bottom protection area of the second conductivity type to be in contact with a bottom of the trench, and

forming a base-bottom embedded region of the second conductivity type inside the semiconductor layer to be in contact with a bottom surface of the base region.

15. The method of claim 14 , wherein the base region is formed by growing a second conductivity type epitaxial layer, and the semiconductor region is implemented by the epitaxial layer.

16. The method of claim 14 , wherein each of the guard rings is formed to have a depth as same as the depth of the base contact region, and the separation regions are formed to have a depth as same as the depth of the source region.

17. The method of claim 14 , wherein the separation regions are formed so that an impurity concentration of second conductivity type impurities contained in each of the guard rings is the same as an impurity concentration of second conductivity type impurities contained in the base contact region and an impurity concentration of first conductivity type impurities contained in each of the separation regions is the same as the impurity concentration of first conductivity type impurities contained in the source region.

18. The method of claim 12 , wherein each of the guard rings has a first region and a second region in contact with a bottom surface of the first region, and the second region is formed to have a width different from that of the first region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 24, 2021
From: OKUMURA, KEIJI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 058202/0811 →
Priority Claims (1)
JP 2021-1061 · Jan 6, 2021 · national
Continuity (1)
Related Publication 20220216335A1 · Jul 7, 2022
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