Reducing crosstalk pessimism using GPU-accelerated gate simulation and machine learning
To facilitate crosstalk analysis for an IC design, a plurality of input vectors are input into a gate-level simulation. In response, the gate-level simulation determines timing windows for all nets within the IC design, may perform aggressor pruning, and may then determine and output aggressor/victim pairs and associated features for the IC design. This gate-level simulation may be accelerated utilizing one or more graphics processor units (GPUs). Additionally, the aggressor/victim pairs and associated features for the IC design are then input into a trained machine learning environment, which outputs predicted delta delays for each of the aggressor/victim pairs. In this way, crosstalk analysis may be performed more accurately and efficiently.
1. A method comprising, at a device:
performing a gate-level simulation of an integrated circuit (IC) design to obtain a plurality of aggressor/victim pairs for the IC design, wherein the gate-level simulation performs at least one of:
logical correlation-based pruning where aggressor nets and victim nets having signal transitions that do not overlap are excluded from the aggressor/victim pairs obtained for the IC design, or
distance-based pruning where aggressor nets and victim nets that switch more than a predetermined time threshold apart from each other are excluded from the aggressor/victim pairs obtained for the IC design; and
processing the plurality of aggressor/victim pairs, by a machine learning model, to predict a delta delay for each of the plurality of aggressor/victim pairs.
2. The method of claim 1 , wherein the IC design includes a partition of an overall IC design.
3. The method of claim 1 , wherein the gate-level simulation is accelerated utilizing one or more graphics processor units (GPUs).
4. The method of claim 1 , wherein a plurality of input vectors are input into the gate-level simulation.
5. The method of claim 1 , wherein given a plurality of input vectors, the gate-level simulation determines timing windows for one or more nets within the IC design.
6. The method of claim 1 , wherein the gate-level simulation determines and outputs aggressor/victim pairs for the IC design, where for each of the output aggressor/victim pairs:
an aggressor net is capacitively coupled with a victim net, and
signal transitions of the aggressor net and the victim net overlap.
7. The method of claim 1 , wherein the gate-level simulation performs the logical correlation-based pruning.
8. The method of claim 1 , wherein the gate-level simulation performs the distance-based pruning.
9. The method of claim 1 , wherein the gate-level simulation determines and outputs associated features for each of the plurality of aggressor/victim pairs, wherein the features for at least one of the aggressor/victim pairs includes one or more of:
a victim slew value,
an aggressor slew value,
a bump value indicating a percentage of a voltage of a victim net that is perturbed due to an aggressor net,
victim load indicating a load capacitance on the victim net, or
a relative distance between switching times of the aggressor net and the victim net.
10. The method of claim 1 , wherein the machine learning model takes each of the plurality of aggressor/victim pairs, as well as associated features for each pair, as input, wherein the features for at least one of the aggressor/victim pairs includes one or more of:
a victim slew value,
an aggressor slew value,
a bump value indicating a percentage of a voltage of a victim net that is perturbed due to an aggressor net,
victim load indicating a load capacitance on the victim net, or a relative distance between switching times of the aggressor net and the victim net.
11. The method of claim 1 , further comprising at the device:
training the machine learning model.
12. A system comprising:
a hardware processor of a device that is configured to:
perform a gate-level simulation of an integrated circuit (IC) design to obtain a plurality of aggressor/victim pairs for the IC design, wherein the gate-level simulation performs at least one of:
logical correlation-based pruning where aggressor nets and victim nets having signal transitions that do not overlap are excluded from the aggressor/victim pairs obtained for the IC design, or
distance-based pruning where aggressor nets and victim nets that switch more than a predetermined time threshold apart from each other are excluded from the aggressor/victim pairs obtained for the IC design; and
process the plurality of aggressor/victim pairs, by a machine learning model, to predict a delta delay for each of the plurality of aggressor/victim pairs.
13. The system of claim 12 , wherein the IC design includes a partition of an overall IC design.
14. The system of claim 12 , wherein the gate-level simulation is accelerated utilizing one or more graphics processor units (GPUs).
15. The system of claim 12 , wherein a plurality of input vectors are input into the gate-level simulation.
16. The system of claim 12 , wherein given a plurality of input vectors, the gate-level simulation determines timing windows for one or more nets within the IC design.
17. The system of claim 12 , wherein the gate-level simulation determines and outputs aggressor/victim pairs for the IC design, based on timing windows for one or more nets within the IC design.
18. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor of a device, causes the processor to cause the device to:
perform a gate-level simulation of an integrated circuit (IC) design to obtain a plurality of aggressor/victim pairs for the IC design, wherein the gate-level simulation performs at least one of:
logical correlation-based pruning where aggressor nets and victim nets having signal transitions that do not overlap are excluded from the aggressor/victim pairs obtained for the IC design, or
distance-based pruning where aggressor nets and victim nets that switch more than a predetermined time threshold apart from each other are excluded from the aggressor/victim pairs obtained for the IC design; and
process the plurality of aggressor/victim pairs, by a machine learning model, to predict a delta delay for each of the plurality of aggressor/victim pairs.
19. The computer-readable storage medium of claim 18 , wherein the gate-level simulation is accelerated utilizing one or more graphics processor units (GPUs).