Oxide semiconductor transistor
Provided are oxide semiconductor transistors. The oxide semiconductor transistor includes a substrate, a channel layer arranged on the substrate and having a flat plate shape extending along one plane, a gate electrode facing a part of the channel layer, and a source region and a drain region separated from each other with the gate electrode therebetween, wherein the source region contacts three or more surfaces of the channel layer, and the drain region contacts three or more surfaces of the channel layer.
1 . An oxide semiconductor transistor comprising:
a substrate;
a channel layer comprising oxide semiconductor material on the substrate;
a gate electrode facing a part of the channel layer; and
a source electrode and a drain electrode that are separated from each other with the gate electrode between the source electrode and the drain electrode; and
a contact unit arranged at least between the source electrode and channel layer or between the drain electrode and the channel layer,
wherein the contact unit includes an electrically conductive material and integrally and contiguously wraps around a first portion of the channel layer to contact at least three surfaces of the channel layer, wherein
the at least three surfaces include three or more of a top surface, a side surface, a bottom surface, the bottom surface opposite to the top surface, a front surface, and a rear surface, the rear surface opposite to the front surface,
wherein the contact unit contacts an upper surface of, a lower surface of, and one side surface of the channel layer.
2 . An oxide semiconductor transistor comprising:
a substrate;
a channel layer comprising oxide semiconductor material on the substrate;
a gate electrode facing a part of the channel layer; and
a source electrode and a drain electrode that are separated from each other with the gate electrode between the source electrode and the drain electrode; and
a contact unit arranged at least between the source electrode and channel layer or between the drain electrode and the channel layer,
wherein the contact unit includes an electrically conductive material and integrally and contiguously wraps around a first portion of the channel layer to contact at least three surfaces of the channel layer, wherein
the at least three surfaces include three or more of a top surface, a side surface, a bottom surface, the bottom surface opposite to the top surface, a front surface, and a rear surface, the rear surface opposite to the front surface,
wherein the contact unit contacts an upper surface of, a lower surface of, the front surface of, and the rear surface of the channel layer.
3 . The oxide semiconductor transistor of claim 1 , further comprising:
a first buffer layer between the channel layer and the contact unit.
4 . The oxide semiconductor transistor of claim 1 ,
wherein the substrate includes an insulating substrate, and the contact unit contacts the substrate.
5 . The oxide semiconductor transistor of claim 1 ,
wherein the substrate includes a conductive substrate, and the contact unit is separated from the substrate.
6 . The oxide semiconductor transistor of claim 5 , further comprising:
an interlayer insulating layer between the substrate and a region including the contact unit.
7 . The oxide semiconductor transistor of claim 1 ,
wherein the gate electrode is on a second surface of the channel layer opposite to a first surface of the channel layer facing the substrate.
8 . The oxide semiconductor transistor of claim 1 ,
wherein the gate electrode is between the channel layer and the substrate.
9 . The oxide semiconductor transistor of claim 1 ,
wherein the gate electrode includes a first gate electrode, and the gate electrode further includes a second gate electrode symmetrically arranged with the first gate electrode with the channel layer therebetween.
10 . The oxide semiconductor transistor of claim 1 , further comprising:
a gate spacer covering a side surface of the gate electrode.
11 . The oxide semiconductor transistor of claim 1 ,
wherein the channel layer has a thickness of about 30 nm or less.
12 . The oxide semiconductor transistor of claim 1 , further comprising:
a gate insulating layer arranged between the channel layer and the gate electrode.
13 . The oxide semiconductor transistor of claim 1 , further comprising:
a first conductive plug contacting the contact unit and extending in one direction.
14 . The oxide semiconductor transistor of claim 13 ,
wherein the first conductive plug extends in a direction perpendicular to a second surface of the channel layer that is opposite to a first surface of the channel layer facing the substrate.
15 . The oxide semiconductor transistor of claim 13 ,
wherein the first conductive plug is between the channel layer and the substrate.
16 . The oxide semiconductor transistor of claim 13 ,
wherein the first conductive plug extends in one direction parallel to the extending direction of the channel layer.
17 . The oxide semiconductor transistor of claim 16 ,
wherein the gate electrode includes a first gate electrode, and the gate electrode further includes a second gate electrode symmetrically arranged with the first gate electrode with the channel layer between the first gate electrode and the second gate electrode.
18 . The oxide semiconductor transistor of claim 13 ,
wherein the channel layer extends in one direction perpendicular to an upper surface of the substrate, and the first conductive plug extends in one direction parallel to the extending direction of the channel layer.
19 . The oxide semiconductor transistor of claim 18 ,
wherein the gate electrode includes a first gate electrode, and the gate electrode further includes a second gate electrode symmetrically arranged with the first gate electrode with the channel layer therebetween.
20 . A memory apparatus comprising a plurality of memory cells,
wherein each memory cell includes,
a switching device, and
a data storage element connected to the switching device, and
the switching device includes,
a channel layer comprising an oxide semiconductor material,
a gate electrode facing a part of the channel layer,
a source electrode and a drain electrode that are separated from each other with the gate electrode between the source electrode and the drain electrode, and
a contact unit arranged at least between the source electrode and channel layer or between the drain electrode and the channel layer,
wherein the contact unit includes an electrically conductive material and contiguous and integrally wraps around a first portion of the channel layer to contact at least three surfaces of the channel layer,
wherein the at least three surfaces include three or more of a top surface, a side surface, a bottom surface, the bottom surface opposite to the top surface a front surface, and a rear surface, the rear surface opposite to the front surface,
wherein the contact unit contacts an upper surface of, a lower surface of, and one side surface of the channel layer.
21 . The oxide semiconductor transistor of claim 2 ,
wherein the contact unit further contacts the front surface of and the rear surface of the channel layer.
22 . The memory apparatus of claim 20 ,
wherein the contact unit contacts a front surface of, and a rear surface of the channel layer.
23 . The memory apparatus of claim 20 ,
wherein the contact unit further contacts a front surface of the channel layer.