Transistor and semiconductor device
View Patent ↗A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.
1. A semiconductor device comprising a transistor, the transistor comprising:
an oxide semiconductor;
a first conductor;
a second conductor;
a third conductor;
a first insulator;
a second insulator; and
a third insulator,
wherein the first conductor comprises a first region, a second region, and a third region,
wherein the first region comprises a region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween,
wherein the second region comprises a region where the first conductor overlaps with the second conductor with the first insulator and the second insulator positioned therebetween, wherein the third region comprises a region where the first conductor overlaps with the third conductor with the first insulator and the second insulator positioned therebetween, wherein a top surface of the second insulator has planarity,
wherein the second insulator has an opening under the first conductor,
wherein the first insulator is provided on the top surface of the second insulator and in the opening of the second insulator, and
wherein the oxide semiconductor is provided on and in contact with a protruding portion of the third insulator.
2. The semiconductor device according to claim 1 ,
wherein the transistor is an n-channel transistor,
wherein the semiconductor device further comprises a p-channel transistor,
wherein one of a source and a drain of the p-channel transistor is electrically connected to one of a source and a drain of the n-channel transistor,
wherein a gate of the p-channel transistor is electrically connected to a gate of the n-channel transistor, and
wherein the p-channel transistor comprises silicon in a channel formation region.
3. The semiconductor device according to claim 2 , wherein the p-channel transistor is formed using a silicon substrate whose crystal plane in its top surface comprises a region of a (110) plane.
4. The semiconductor device according to claim 2 , wherein the channel formation region of the p-channel transistor has a concentration gradient such that a concentration of an impurity imparting an n-type conductivity gets higher toward a vicinity of a surface of the channel formation region.
5. The semiconductor device according to claim 2 , wherein the gate of the p-channel transistor comprises a conductor with a work function of 4.5 eV or higher.
6. The semiconductor device according to claim 1 , wherein the oxide semiconductor comprises indium.
7. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor comprises a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer, and
wherein the oxide semiconductor comprises a region where the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer overlap with each other.
8. The semiconductor device according to claim 1 , wherein the first insulator is in contact with the oxide semiconductor through the opening in the second insulator.
9. The semiconductor device according to claim 1 , wherein an end portion of the first conductor and an end portion of the first insulator are aligned with each other.
10. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor comprises a fourth region and a fifth region,
wherein the fourth region comprises a region where the oxide semiconductor is in contact with the second conductor, and
wherein the fifth region comprises a region where the oxide semiconductor is in contact with the third conductor.
11. A semiconductor device comprising a first transistor, the first transistor comprising:
an oxide semiconductor;
a first conductor over the oxide semiconductor;
a second conductor and a third conductor on the oxide semiconductor; and
a first insulator on the oxide semiconductor;
a second insulator on the second conductor and the third conductor and under the first insulator, a top surface of the second insulator having planarity; and
a third insulator under the oxide semiconductor,
wherein the first conductor comprises:
a first region overlapping with the oxide semiconductor with the first insulator positioned therebetween;
a second region overlapping with the second conductor with the first insulator and the second insulator positioned therebetween; and
a third region overlapping with the third conductor with the first insulator and the second insulator positioned therebetween,
wherein the second insulator has an opening under the first conductor,
wherein the first insulator is provided on the top surface of the second insulator and in the opening of the second insulator, and
wherein the third insulator has a protruding portion in a region in contact with the oxide semiconductor.
12. The semiconductor device according to claim 11 , further comprising a second transistor,
wherein one of a source and a drain of the second transistor is electrically connected to one of the second conductor and the third conductor of the first transistor,
wherein a gate of the second transistor is electrically connected to the first conductor of the first transistor.
13. The semiconductor device according to claim 12 , wherein the second transistor is formed using a silicon substrate whose crystal plane in its top surface comprises a region of a (110) plane.
14. The semiconductor device according to claim 12 , wherein a channel formation region of the second transistor has a concentration gradient such that a concentration of an impurity imparting an n-type conductivity gets higher toward a vicinity of a surface of the channel formation region.
15. The semiconductor device according to claim 12 , wherein the gate of the second transistor comprises a conductor with a work function of 4.5 eV or higher.
16. The semiconductor device according to claim 12 , wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor.
17. The semiconductor device according to claim 11 , wherein the oxide semiconductor comprises indium.
18. The semiconductor device according to claim 11 ,
wherein the oxide semiconductor comprises a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer, and
wherein the oxide semiconductor comprises a region where the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer overlap with each other.
19. The semiconductor device according to claim 11 , wherein the first insulator is in contact with the oxide semiconductor through the opening in the second insulator.
20. The semiconductor device according to claim 11 , wherein an end portion of the first conductor and an end portion of the first insulator are aligned with each other.
21. The semiconductor device according to claim 11 ,
wherein the oxide semiconductor comprises: a fourth region being in contact with the second conductor; and a fifth region being in contact with the third conductor.