Semiconductor device and manufacturing method thereof

1. A method of manufacturing a semiconductor device, the method comprising:

forming, on a carrier top side of a carrier, layers of an upper signal distribution structure;

coupling a bottom side of a semiconductor component to a top side of the upper signal distribution structure; and

after coupling the semiconductor component, forming, on a bottom side of the upper signal distribution structure, layers of a lower signal distribution structure;

wherein the layers of the lower signal distribution structure include a first dielectric layer and a first conductive layer;

wherein the first conductive layer of the lower signal distribution structure extends into a first opening in the first dielectric layer of the lower signal distribution structure and towards the upper signal distribution structures;

wherein the lower signal distribution structure comprises an under bump metal structure that has a concave shape that opens downward;

wherein the under bump metal structure comprises a bump upper side and a bump lower side; and

wherein the bump upper side is coupled to a bottom side of the lower signal distribution structure.

2. The method of claim 1 , wherein:

the layers of the upper signal distribution structure include a first dielectric layer and a first conductive layer; and

the first conductive layer of the upper signal distribution structure extends into an opening in the first dielectric layer of the upper signal distribution structure and towards the lower signal distribution structure.

3. The method of claim 1 , wherein forming the layers of the upper signal distribution structure comprises:

forming a first dielectric layer of the upper signal distribution structure;

forming a first conductive layer of the upper signal distribution structure on the first dielectric layer of the upper signal distribution structure such that the first conductive layer of the upper signal distribution structure extends into a first opening in the first dielectric layer of the upper signal distribution structure and towards the lower signal distribution structure;

forming a second dielectric layer of the upper signal distribution structure on the first conductive layer of the upper signal distribution structure; and

forming a second conductive layer of the upper signal distribution structure on the second dielectric layer of the upper signal distribution structure such that the second conductive layer of the upper signal distribution structure extends into a second opening in the second dielectric layer of the upper signal distribution structure and towards the lower signal distribution structure.

4. The method of claim 1 , wherein forming the layers of the lower signal distribution structure comprises:

forming a second dielectric layer of the lower signal distribution structure on the first conductive layer of the lower signal distribution structure; and

forming a second conductive layer of the lower signal distribution structure on the second dielectric layer of the lower signal distribution structure such that the second conductive layer of the lower signal distribution structure extends into a second opening in the second dielectric layer of the lower signal distribution structure and towards the upper signal distribution structure.

5. The method of claim 1 , wherein the upper signal distribution structure and the lower signal distribution structure lack through silicon vias.

6. The method of claim 1 , wherein the carrier comprises a glass.

7. The method of claim 1 , wherein the carrier comprises a semiconductor carrier.

8. The method of claim 1 , comprising:

forming a bump pad that is coupled to a first conductive layer of the layers of the upper signal distribution structure; and

wherein coupling the semiconductor component comprises coupling a conductive bump of the semiconductor component to the bump pad.

9. A semiconductor device comprising:

an upper signal distribution structure comprising an upper structure top side and an upper structure bottom side;

a lower signal distribution structure comprising a lower structure top side and a lower structure bottom side, wherein the upper structure bottom side is coupled to the lower structure top side;

a semiconductor component comprising a component top side and a component bottom side, wherein the component bottom side is coupled to the upper structure top side; and

a conductive interconnection structure coupled to the lower structure bottom side; and

wherein the lower signal distribution structure comprises a dielectric lower layer and a conductive lower layer;

wherein the conductive lower layer extends into an opening in the dielectric lower layer and towards the upper signal distribution structure;

wherein the lower signal distribution structure comprises an under bump metal structure that has a concave shape that opens downward;

wherein the under bump metal structure comprises a bump upper side and a bump lower side; and

wherein the bump upper side is coupled to the lower structure bottom side.

10. The semiconductor device of claim 9 , wherein:

the upper signal distribution structure comprises a dielectric upper layer and a conductive upper layer; and

the conductive upper layer extends into an opening in the dielectric upper layer and towards the lower signal distribution structure.

11. The semiconductor device of claim 9 , wherein:

the upper signal distribution structure comprises an upper conductive via;

the upper conductive via comprises a seed upper layer and a plated upper layer on an upper side of the seed upper layer;

the conductive lower layer comprises a lower conductive via; and

the lower conductive via comprises a seed lower layer and a plated lower layer on a lower side of the seed lower layer.

12. The semiconductor device of claim 11 , wherein:

the under bump metal structure is laterally wider than the lower conductive via;

the lower conductive via is laterally wider than the upper conductive via.

13. The semiconductor device of claim 9 , comprising conductive bumps that couple the component bottom side to the upper structure top side.

14. The semiconductor device of claim 9 , comprising a mold material that encapsulates the semiconductor component and the upper structure top side.

15. A method of manufacturing a semiconductor device, the method comprising:

providing a first structure comprising:

a support structure;

a semiconductor component comprising:

a component top side coupled to the support structure and facing a first direction;

a component bottom side opposite the component top side and facing a second direction; and

a component pad at the component front bottom side;

a conductive pillar that is coupled to the component pad and extends in the second direction from the component pad;

an encapsulating material comprising an encapsulant top side and an encapsulant bottom side opposite the encapsulant top side, wherein the encapsulant top side faces the support structure, and wherein the encapsulating material laterally surrounds the semiconductor component and the conductive pillar; and

an upper signal distribution structure over the the component bottom side and over the encapsulant bottom side, wherein the upper signal distribution structure comprises an upper signal distribution structure top side facing the first direction and an upper signal distribution structure bottom side facing the second direction;

forming a lower signal distribution structure comprising a lower signal distribution structure top side coupled to the upper signal distribution structure top side;

wherein forming the lower signal distribution structure comprises sequentially forming layers of the lower signal distribution structure in the second direction such that a conductive layer of the lower signal distribution structure extends into an opening of a dielectric layer of the lower signal distribution structure and towards the upper signal distribution structure; wherein the lower signal distribution structure comprises an under bump metal structure that has a concave shape that opens downward;

wherein the under bump metal structure comprises a bump upper side and a bump lower side; and

wherein the bump upper side is coupled to a bottom side of the lower signal distribution structure.

16. The method of claim 15 , wherein the first upper signal distribution structure comprises:

a dielectric layer comprising a dielectric layer top side and a dielectric layer bottom side opposite the dielectric layer top side, wherein the dielectric layer top side faces toward the semiconductor component and the encapsulating material; and

a conductive layer comprising;

a conductive via, and

a horizontal trace on the dielectric layer bottom side;

wherein the conductive via extends through the dielectric layer from the dielectric layer bottom side toward the dielectric layer top side; and

wherein the horizontal trace is connected to the conductive via.

17. The method of claim 16 , wherein the dielectric layer of the upper signal distribution structure laterally surrounds the conductive via but not the horizontal trace.

18. The method of claim 17 , wherein:

the under bump metal structure is coupled to the horizontal trace; and

the lower signal distribution structure comprises a second dielectric layer that laterally surrounds the horizontal trace and that laterally surrounds a portion of the under bump metal structure.