IP Library Granted Patent US 12,648,479
Granted Patent B2
US 12,648,479 · App. 17/545,040 · Granted Jun 2, 2026

Semiconductor module manufacturing method, electronic equipment manufacturing method, semiconductor module, and electronic equipment

Inventors: Kana Onoko (Kanagawa, JP); Takashi Aoki (Chiba, JP)
Assignee: Canon Kabushiki Kaisha
H10W90/00H10W72/071H10W90/701H10W72/072
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Quick Facts
Patent No.
US 12,648,479
App. No.
17/545,040
Filed
Dec 8, 2021
Granted
Jun 2, 2026
Kind
B2
Art Unit
2893
USPC
257/738
Abstract

A chip component including a first electrode and a second electrode, a semiconductor device including a first land and a second land, and a printed wiring board are prepared. A first solder paste and a second solder paste are supplied to the printed wiring board. The chip component is placed on the printed wiring board so that the first electrode is in contact with the first solder paste and the second electrode is in contact with the second solder paste. The semiconductor device is placed on the printed wiring board so that the first land faces the first electrode and the second land faces the second electrode. The solder paste is heated and melted, the first land and the first electrode are bonded to each other, and the second land and the second electrode are bonded to each other.

Claims (50)

1 . A semiconductor module comprising:

a printed wiring board;

a semiconductor device comprising a first land and a second land, the semiconductor device being mounted on the printed wiring board;

a chip component comprising a first electrode and a second electrode spaced apart from each other in a predetermined direction, the chip component being disposed between the printed wiring board and the semiconductor device;

a first solder bonding portion that bonds the first electrode and the first land to each other; and

a second solder bonding portion that bonds the second electrode and the second land to each other,

wherein the printed wiring board comprises an insulating substrate and a solder resist disposed on a main surface of the insulating substrate,

wherein the chip component faces the solder resist,

wherein each of the first land and the second land overlaps at least a portion of each of the first electrode and the second electrode in a plan view and extends outward in the predetermined direction from the chip component,

wherein the first solder bonding portion has a fillet shape in which the first solder bonding portion spreads outward in the predetermined direction such that the first solder bonding portion extends longer in the predetermined direction in a part of the first solder bonding portion that is adjacent to the first land than in a part of the first solder bonding portion that is most distant from the first land, and

wherein wettability of the first land with molten solder is higher than wettability of the first electrode with molten solder.

2 . The semiconductor module according to claim 1 , wherein the first land is a power terminal, and the second land is a ground terminal.

3 . The semiconductor module according to claim 1 , wherein the chip component is a chip component of 0402 size or less.

4 . The semiconductor module according to claim 1 , wherein the chip component is a capacitor.

5 . The semiconductor module according to claim 1 , wherein the semiconductor device is a BGA semiconductor package in which an interval between lands is 0.4 mm or less.

6 . The semiconductor module according to claim 1 , wherein the semiconductor device comprises a semiconductor element, and the semiconductor element and the chip component overlap each other in a plan view of the semiconductor module.

7 . The semiconductor module according to claim 1 , further comprising, a third solder bonding portion that bonds a fifth land and a sixth land,

wherein the semiconductor device comprises the fifth land,

wherein the printed wiring board comprises the sixth land on a main surface of the insulating substrate, and

wherein a height of the third solder bonding portion is greater than a height of the chip component.

8 . Electronic equipment comprising:

a casing; and

the semiconductor module according to claim 1 disposed inside the casing.

9 . The semiconductor module according to claim 1 , wherein the second solder bonding portion has a fillet shape in which the second solder bonding portion spreads outward in the predetermined direction such that the second solder bonding portion extends longer in the predetermined direction in a part of the second solder bonding portion that is adjacent to the second land than in a part of the second solder bonding portion that is most distant from the second land, and

wherein wettability of the second land with molten solder is higher than wettability of the second electrode with molten solder.

10 . A semiconductor module comprising:

a printed wiring board;

a semiconductor device comprising a first land and a second land, the semiconductor device being mounted on the printed wiring board;

a chip component comprising a first electrode and a second electrode spaced apart from each other in a predetermined direction, the chip component being disposed between the printed wiring board and the semiconductor device;

a first solder bonding portion that bonds the first electrode and the first land to each other; and

a second solder bonding portion that bonds the second electrode and the second land to each other,

wherein the printed wiring board comprises an insulating substrate, a third land disposed on a main surface of the insulating substrate and electrically connected to the first land by the first solder bonding portion, and a fourth land disposed on the main surface of the insulating substrate and electrically connected to the second land by the second solder bonding portion,

wherein, in a plan view, each of the first land and the second land overlaps at least a portion of each of the first electrode and the second electrode, overlaps at least a portion of each of the third land and the fourth land, and extends outward in the predetermined direction from the chip component,

wherein the first solder bonding portion has a fillet shape in which the first solder bonding portion spreads outward in the predetermined direction such that the first solder bonding portion extends longer in the predetermined direction in a part of the first solder bonding portion that is adjacent to the first land than in a part of the first solder bonding portion that is adjacent to the third land, and

wherein, in a plan view, an area of the first land is larger than an area of the third land.

11 . The semiconductor module according to claim 10 , wherein the second solder bonding portion has a fillet shape in which the second solder bonding portion spreads outward in the predetermined direction such that the second solder bonding portion extends longer in the predetermined direction in a part of the second solder bonding portion that is adjacent to the second land than in a part of the second solder bonding portion that is adjacent to the fourth land, and

wherein in a plan view, an area of the second land is larger than area of the fourth land.

12 . A semiconductor module comprising:

a printed wiring board;

a semiconductor device comprising a first land and a second land, the semiconductor device being mounted on the printed wiring board;

a chip component comprising a first electrode and a second electrode spaced apart from each other in a predetermined direction, the chip component being disposed between the printed wiring board and the semiconductor device;

a first solder bonding portion that bonds the first electrode and the first land to each other; and

a second solder bonding portion that bonds the second electrode and the second land to each other,

wherein the printed wiring board comprises an insulating substrate and a solder resist disposed on a main surface of the insulating substrate,

wherein the solder resist has an opening portion into which a portion of the chip component is inserted,

wherein each of the first land and the second land overlaps at least a portion of each of the first electrode and the second electrode in a plan view and extends outward in the predetermined direction from the chip component,

wherein the first solder bonding portion has a fillet shape in which the first solder bonding portion spreads outward in the predetermined direction such that the first solder bonding portion extends longer in the predetermined direction in a part of the first solder bonding portion that is adjacent to the first land than in a part of the first solder bonding portion that is adjacent to the portion of the main surface of the insulating substrate exposed by the opening portion of the solder resist, and

wherein wettability of the first land with molten solder is higher than wettability of the first electrode with molten solder.

13 . The semiconductor module according to claim 12 , wherein the second solder bonding portion has a fillet shape in which the second solder bonding portion spreads outward in the predetermined direction such that the second solder bonding portion extends longer in the predetermined direction in a part of the second solder bonding portion that is adjacent to the second land than in a part of the second solder bonding portion that is adjacent to the portion of the main surface of the insulating substrate exposed by the opening portion of the solder resist, and

wherein wettability of the second land with molten solder is higher than wettability of the second electrode with molten solder.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 26, 2021
From: ONOKO, KANA; AOKI, TAKASHI
To: CANON KABUSHIKI KAISHA
Reel/Frame 058477/0426 →
Priority Claims (2)
JP 2019-110913 · Jun 14, 2019 · national
JP 2020-088291 · May 20, 2020 · national
Continuity (2)
Continuation PCTJP2020022914 · Jun 10, 2020
Related Publication 20220102330A1 · Mar 31, 2022
References Cited (26)
US 7697582B2 · Aoki · 2010 [cited by applicant]
US 9648739B2 · Aoki · 2017 [cited by examiner]
US 20020159243A1 · Ogawa · 2002 [cited by examiner]
US 20060108607A1 · Teshima et al. · 2006 [cited by applicant]
US 20110120769A1 · Sakatani · 2011 [cited by examiner]
US 20140197530A1 · Meyer · 2014 [cited by examiner]
US 20150092356A1 · Yoshikawa · 2015 [cited by examiner]
US 20150163925A1 · Nakatsuji · 2015 [cited by examiner]
US 20170181286A1 · Campbell et al. · 2017 [cited by applicant]
US 20180374790A1 · Chang et al. · 2018 [cited by applicant]
US 20200051887A1 · Aoki · 2020 [cited by applicant]
JP 10163263 · 1996 [cited by examiner]
JP H10163263A · 1998 [cited by applicant]
JP 2001257445A · 2001 [cited by applicant]
JP 2002280704 · 2002 [cited by examiner]
JP 2002280704A · 2002 [cited by applicant]
JP 2004228364A · 2004 [cited by applicant]
JP 2005150283 · 2005 [cited by examiner]
JP 20050150283 · 2005 [cited by examiner]
JP 2005150283A · 2005 [cited by applicant]
JP 2006173407A · 2006 [cited by applicant]
JP 2018137276A · 2018 [cited by applicant]
Jun. 25, 2024 Office Action in Japanese Patent Application Pub. No. 2020-088291 (with English translation). [cited by applicant]
International Search Report and Written Opinion for International Patent Application No. PCT/JP2020/022914. [cited by applicant]
Mar. 25, 2025 Office Action in Chinese Patent Application Pub. No. 202080043396.1 (with English translation). [cited by applicant]
Nov. 19, 2025 Office Action in Chinese Patent Application Pub. No. 202080043396.1. [cited by applicant]