Granted Patent B2

US 12,445,532 · App. 17/545,730 · Granted Oct 14, 2025

Inventors: Isaac R. Nassi (Los Gatos, CA); David P. Reed (Needham, MA)

Assignee: Hewlett Packard Enterprise Development LP

H04L67/568G06F9/45558G06F12/0815H04L67/10H04L67/1097H04L67/2885G06F2009/45583

Abstract

Claims (27)

1. A computer system, comprising:

a plurality of interconnected computing nodes, wherein a guest operating system is run on a virtual environment that is defined by a set of hyper-kernels running on at least a portion of the interconnected computing nodes;

a persistent memory array separate from the plurality of interconnected computing nodes and separate from the virtual environment, wherein the persistent memory array communicates with at least some of the computing nodes over a network according to a coherency protocol;

wherein, based at least in part on an operation to be performed with respect to a portion of memory on a first computing node included in the plurality of interconnected computing nodes, the persistent memory array receives, in accordance with the coherency protocol, a message, and wherein the portion of memory on the first computing node corresponds to a guest physical address in the virtual environment; and

wherein the persistent memory array is configured to perform an action based at least in part on the coherency protocol and the received message.

2. The computer system of claim 1 , wherein portions of the persistent memory array correspond to guest physical addresses in the virtual environment defined by the set of hyper-kernels running on the at least portion of the interconnected computing nodes.

3. The computer system of claim 1 , wherein the operation to be performed with respect to the portion of memory on the first computing node comprises writing into the portion of memory.

4. The computer system of claim 3 , wherein the message comprises an invalidation request.

5. The computer system of claim 4 , wherein the action performed by the persistent memory array comprises invalidating a copy of the portion of memory stored on the persistent memory array.

6. The computer system of claim 5 , wherein the persistent memory array is configured to return an acknowledgment indicating completion of the invalidation.

7. The computer system of claim 6 , wherein the writing into the portion of memory is performed based at least in part on the returned acknowledgment.

8. The computer system of claim 1 , wherein the operation to be performed with respect to the portion of memory on the first computing node comprises a read request for the portion of memory.

9. The computer system of claim 8 , wherein the action performed by the persistent memory array comprises receiving a copy of the portion of memory.

10. The computer system of claim 1 , wherein in response to detection of a failure, the persistent memory array is configured to request copies of one or more portions of memory from the computing nodes in the plurality of interconnected computing nodes.

11. The computer system of claim 10 , wherein the one or more portions of memory for which copies are requested comprise portions of memory determined to be invalid on the persistent memory array.

12. The computer system of claim 11 , wherein the persistent memory array is configured to update an invalid portion of memory with a corresponding obtained copy of a requested page.

13. The computer system of claim 1 , wherein the persistent memory array comprises a centralized appliance.

14. The computer system of claim 1 , wherein the persistent memory array includes at least one of flash memory, phase change memory, and 3D-Xpoint memory.

15. The computer system of claim 1 , wherein the persistent memory array is configured to store a read-only copy of the portion of memory.

16. A method, comprising:

receiving, at a persistent memory array, a message, wherein the message is received in accordance with a coherency protocol, and wherein the message is received based at least in part on an operation to be performed with respect to a portion of memory on a first computing node in a plurality of interconnected computing nodes;

wherein a guest operating system is run on a virtual environment that is defined by a set of hyper-kernels running on at least a portion of the interconnected computing nodes, the persistent memory array is separate from the interconnected computing nodes, the persistent memory array is separate from the virtual environment, and wherein the persistent memory array communicates with at least some of the computing nodes over a network according to the coherency protocol; and

performing, by the persistent memory array, an action based at least in part on the coherency protocol and the received message.

17. A computer program product embodied in a non-transitory computer readable storage medium and comprising computer instructions for:

receiving, at a persistent memory array, a message, wherein the message is received in accordance with a coherency protocol, and wherein the message is received based at least in part on an operation to be performed with respect to a portion of memory on a first computing node in a plurality of interconnected computing nodes;

wherein a guest operating system is run on a virtual environment that is defined by a set of hyper-kernels running on at least a portion of the interconnected computing nodes, the persistent memory array is separate from the interconnected computing nodes, the persistent memory array is separate from the virtual environment, and wherein the persistent memory array communicates with at least some of the computing nodes over a network according to the coherency protocol; and

performing, by the persistent memory array, an action based at least in part on the coherency protocol and the received message.

Assignments (2)

Continuity (3)

References Cited (359)