Store-operate-coherence-on-value

1. A method for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device, the method comprising:

receiving, from a processor, a store-operate instruction that specifies a condition under which a cache coherence operation is to be invoked, said condition being a particular value that is in the received instruction from the processor, the received instruction specifying the particular value as zero;

running the received store-operate instruction to obtain a result value;

evaluating whether the result value of the running the received store-operate instruction is the particular value;

invoking a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result value is the particular value; and

otherwise, not invoking the cache coherence operation on the cache memory device,

wherein the parallel computing environment includes a network in which packets are communicated out-of-order among the processors and delivered out-of-order to a network adaptor, a counter that decrements a counter value upon receiving a packet, and the network adaptor that issues a StoreAddCoherenceOnZero instruction, at least one cache memory device in responding to the issued StoreAddCoherenceOnZero instruction to perform the cache coherence operation only when the counter value becomes zero and to avoid or omit performance of the cache coherence operation on an arrival of each packet.

2. The method according to claim 1 , further comprising:

issuing a FetchAndDecrementCoherenceOnZero instruction to implement a barrier which, except for a last arriving thread, does not invoke a cache coherence operation on an arrival of each thread into the barrier.

3. The method according to claim 1 , wherein if the received instruction is a StoreOperateCoherenceOnPredecessor or FetchAndOperateCoherenceOnPredecessor instruction, the method further comprises:

retrieving another value, from the cache memory device, in a preceding memory location of the cache memory address corresponding the logical address;

evaluating whether the result is equal to the retrieved value;

determining that the condition is true if the result is equal to the retrieved value;

determining that the condition is false, otherwise; and

invoking the cache coherence operation only if the condition is true.

4. The method according to claim 1 , wherein if the received instruction is a StoreOperateCoherenceThroughZero or FetchAndOperateCoherenceThroughZero instruction, the method further comprises:

evaluating a sign of the result and a sign of an original data value in the cache memory address;

determining that the condition is true if the sign of the result is an opposite of the sign of the original data value;

determining that the condition is false, otherwise; and

invoking the cache coherence operation only if the condition is true.

5. The method according to claim 1 , wherein the received instruction is one or more of: StoreOperateCoherenceOnValue instruction, StoreOperateCoherenceOnPredecessor instruction, StoreOperateCoherenceThroughZero instruction, FetchAndOperateCoherenceOnValue instruction, FetchAndOperateCoherenceOnPredecessor instruction, and FetchAndOperateCoherenceThroughZero instruction, each received instruction further specifies one or more operations of StoreAdd, StoreMin, StoreMax, each with variations for signed integers, unsigned integers or floating point numbers, Bitwise StoreAnd, Bitwise StoreOr, Bitwise StoreXor, FetchAndIncrement, FetchAndDecrement, and FetchAndClear.

6. A system for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device, the method comprising:

a queue receiving, from a processor, a store-operate instruction that specifies a condition under which a cache coherence operation is to be invoked, said condition being a particular value that is in the received instruction from the processor, the received instruction specifying the particular value as zero;

a hardware unit fetching the received store-operate instruction from the queue, running the received store-operate instruction to obtain a result value, evaluating whether the result value of the running the received store-operate instruction is the particular value, and invoking a cache coherence operation on a cache memory address associated with the received store-operate instruction only if the result value is the particular value;

a network in which packets are communicated out-of-order among the processors and delivered out-of-order to a network adaptor;

a counter decrementing a counter value upon receiving a packet; and

the network adaptor issuing a StoreAddCoherenceOnZero instruction, at least one cache memory device in responding to the issued StoreAddCoherenceOnZero instruction to perform the cache coherence operation only when the counter value becomes zero and to otherwise avoid or omit performance of the cache coherence operation on an arrival of each packet.

7. The system according to claim 6 , wherein the processor issues a FetchAndDecrementCoherenceOnZero instruction to implement a barrier which, except for a last arriving thread, does not invoke a cache coherence operation on an arrival of each thread into the barrier.

8. The system according to claim 6 , wherein if the received instruction is a StoreOperateCoherenceOnPredecessor or FetchAndOperateCoherenceOnPredecessor instruction, the hardware unit is configured to:

retrieve another value, from the cache memory device, in a preceding memory location of the cache memory address corresponding the logical address;

evaluate whether the result is equal to the retrieved value;

determine that the condition is true if the result is equal to the retrieved value;

determine that the condition is false, otherwise; and

invoke the cache coherence operation only if the condition is true.

9. The system according to claim 6 , wherein if the received instruction is a StoreOperateCoherenceThroughZero or FetchAndOperateCoherenceThroughZero instruction, the hardware unit is configured to:

evaluate a sign of the result and a sign of an original data value in the cache memory address;

determine that the condition is true if the sign of the result is an opposite of the sign of the original data value;

determine that the condition is false, otherwise; and

invoke the cache coherence operation only if the condition is true.

10. The system according to claim 6 , wherein the received instruction is one or more of: StoreOperateCoherenceOnValue instruction, StoreOperateCoherenceOnPredecessor instruction, StoreOperateCoherenceThroughZero instruction, FetchAndOperateCoherenceOnValue instruction, FetchAndOperateCoherenceOnPredecessor instruction, and FetchAndOperateCoherenceThroughZero instruction, each received instruction further specifies one or more operations of StoreAdd, StoreMin, StoreMax, each with variations for signed integers, unsigned integers or floating point numbers, Bitwise StoreAnd, Bitwise StoreOr, Bitwise StoreXor, FetchAndIncrement, FetchAndDecrement, and FetchAndClear.

11. A computer program device for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device, the computer program device comprising a storage medium, said storage medium not a propagating signal, said storage medium readable by the processors and storing instructions run by the processors for performing a method, the method comprising:

receiving, from a processor, a store-operate instruction that specifies a condition under which a cache coherence operation is to be invoked, said condition being a particular value that is in the received instruction from the processor, the received instruction specifying the particular value as zero;

running the received store-operate instruction to obtain a result value;

evaluating whether the result value of the running the received store-operate instruction is the particular value;

invoking a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result value is the particular value; and

otherwise, not invoking the cache coherence operation on the cache memory device,

wherein the parallel computing environment includes a network in which packets are communicated out-of-order among the processors and delivered out-of-order to a network adaptor, a counter that decrements a counter value upon receiving a packet, and the network adaptor that issues a StoreAddCoherenceOnZero instruction, at least one cache memory device in responding to the issued StoreAddCoherenceOnZero instruction to perform the cache coherence operation only when the counter value becomes zero and to otherwise avoid or omit performance of the cache coherence operation on an arrival of each packet.

12. The computer program device according to claim 11 , wherein the processor issues a FetchAndDecrementCoherenceOnZero instruction to implement a barrier which, except for the last arriving thread, does not invoke a cache coherence operation on an arrival of each thread into the barrier.

13. The computer program device according to claim 11 , wherein if the received instruction is a StoreOperateCoherenceOnPredecessor or FetchAndOperateCoherenceOnPredecessor instruction, the method further comprises:

retrieving another value, from the cache memory device, in a preceding memory location of the cache memory address corresponding the logical address;

evaluating whether the result is equal to the retrieved value;

determining that the condition is true if the result is equal to the retrieved value;

determining that the condition is false, otherwise; and

invoking the cache coherence operation only if the condition is true.

14. The computer program device according to claim 11 , wherein if the received instruction is a StoreOperateCoherenceThroughZero or FetchAndOperateCoherenceThroughZero instruction, the method further comprises:

evaluating a sign of the result and a sign of an original data value in the cache memory address;

determining that the condition is true if the sign of the result is an opposite of the sign of the original data value;

determining that the condition is false, otherwise; and

invoking the cache coherence operation only if the condition is true.

15. The computer program device according to claim 11 , wherein the received instruction is one or more of: StoreOperateCoherenceOnValue instruction, StoreOperateCoherenceOnPredecessor instruction, StoreOperateCoherenceThroughZero instruction, FetchAndOperateCoherenceOnValue instruction, FetchAndOperateCoherenceOnPredecessor instruction, and FetchAndOperateCoherenceThroughZero instruction, each received instruction further specifies one or more operations of StoreAdd, StoreMin, StoreMax, each with variations for signed integers, unsigned integers or floating point numbers, Bitwise StoreAnd, Bitwise StoreOr, Bitwise StoreXor, FetchAndIncrement, FetchAndDecrement, and FetchAndClear.