Method of making semiconductor device which includes Fins

1. A method of manufacturing fins for a semiconductor device, the method comprising:

forming a first layer on a semiconductor substrate, the first layer having first spacers and etch stop layer (ESL) portions which are interspersed;

forming second spacers on central regions correspondingly of the first spacers and the ESL portions;

removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate;

removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins, the first and second capped semiconductor fins being organized into at least first and second sets;

each member of the first set having a first cap with a first etch sensitivity; and

each member of the second set having a second cap with a second etch sensitivity, the second etch sensitivity being different than the first etch sensitivity; and

eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.

2. The method of claim 1 , wherein the forming a first layer includes:

forming first mandrel features spaced apart on the semiconductor substrate resulting in first exposed regions of the semiconductor substrate;

forming the first spacers on portions of the first exposed regions of the semiconductor substrate and correspondingly abutting sidewalls of the first mandrel features resulting in second exposed regions of the semiconductor substrate;

removing the first mandrel features resulting in third exposed areas of the semiconductor substrate; and

forming the ESL portions on the third exposed areas of the semiconductor substrate and correspondingly abutting sidewalls of the first mandrel features resulting in a second layer.

3. The method of claim 2 , wherein:

relative to a reference direction parallel to a plane of the semiconductor substrate, a width of a representative one of the second exposed regions of the semiconductor substrate is smaller than a width of a representative one of the first exposed regions of the semiconductor substrate.

4. The method of claim 3 , wherein:

the width of the representative one of the second exposed regions of the semiconductor substrate is about one third of the width of the representative one of the first exposed regions of the semiconductor substrate.

5. The method of claim 2 , wherein:

relative to a reference direction parallel to a plane of the semiconductor substrate, a width of a representative one of the first spacers is about the same as a width of a representative one of the first mandrel features.

6. The method of claim 2 , wherein the forming second spacers includes:

forming second mandrel features spaced apart on selected abutting regions correspondingly of the first spacers and the ESL portions resulting in first exposed regions of the second layer, the selected abutting regions correspondingly of the first spacers and the ESL portions being in the first exposed regions;

forming the second spacers to abut corresponding sidewalls of the second mandrel features in addition to the second spacers being on the selected abutting regions correspondingly of the first spacers and the ESL portions resulting in second exposed regions of the second layer; and

removing the second mandrel features resulting in third exposed regions of the second layer.

7. The method of claim 6 , wherein:

relative to a reference direction parallel to a plane of the semiconductor substrate:

a width of a representative one of the second spacers is smaller than a width of a representative one of the second mandrel features; and

a width of a representative one of the second exposed regions of the second layer is smaller than a width of a representative one of the first exposed regions of the second layer.

8. The method of claim 1 , wherein:

relative to a reference direction parallel to a plane of the semiconductor substrate, a width of a representative one of the first spacers is substantially the same as a width of a representative one of the ESL portions.

9. A method of manufacturing fins for a semiconductor device, the method comprising:

forming a first layer on a semiconductor substrate, the first layer having first spacers, second spacers and first etch stop layer (ESL) portions which are interspersed;

forming second ESL portions correspondingly on the first spacers and the first ESL portions;

removing the second spacers;

removing exposed regions of the first spacers and the first ESL portions and corresponding underlying portions of the semiconductor substrate;

removing the second ESL portions resulting in corresponding first capped semiconductor fins and second capped semiconductor fins, the first and second capped semiconductor fins being organized into at least first and second sets;

each member of the first set having a first cap with a first etch sensitivity; and

each member of the second set having a second cap with a second etch sensitivity, the second etch sensitivity being different than the first etch sensitivity; and

eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.

10. The method of claim 9 , wherein the first spacers, the second spacers and the first ESL portions are interspersed such that:

each of the first spacers and is abutted by corresponding ones of the second spacers; and

each of the first ESL portions is abutted by corresponding ones of the second spacers.

11. The method of claim 9 , wherein the forming a first layer includes:

forming first mandrel features spaced apart on the semiconductor substrate resulting in first exposed regions of the semiconductor substrate;

forming fourth spacers on portions of the first exposed regions of the semiconductor substrate and correspondingly abutting sidewalls of the first mandrel features resulting in second exposed regions of the semiconductor substrate;

removing the first mandrel features resulting in third exposed regions of the semiconductor substrate;

forming the first spacers on portions of the third exposed regions of the semiconductor substrate and correspondingly abutting sidewalls of the fourth spacers;

removing the fourth spacers resulting in fourth exposed areas of the semiconductor substrate;

forming the second spacers on portions of the third exposed regions of the semiconductor substrate and correspondingly abutting sidewalls of the second spacers resulting in fifth exposed regions of the semiconductor substrate; and

forming the first ESL portions on the fifth exposed areas of the semiconductor substrate and correspondingly abutting sidewalls of the second spacers resulting in a second layer.

12. The method of claim 11 , wherein:

relative to a reference direction parallel to a plane of the semiconductor substrate, a width of a representative one of the second exposed regions of the semiconductor substrate is smaller than a width of a representative one of the first exposed regions of the semiconductor substrate.

13. The method of claim 12 , wherein:

the width of the representative one of the second exposed regions of the semiconductor substrate is about the same as a width of a representative one of the first mandrel features.

14. The method of claim 11 , wherein:

relative to a reference direction parallel to a plane of the semiconductor substrate, a width of a representative one of the first spacers is less than a width of a representative one of the fourth spacers.

15. The method of claim 11 , wherein:

relative to a reference direction parallel to a plane of the semiconductor substrate, a width of a representative one of the fourth spacers is less than a width of a representative one of the first mandrel features.

16. The method of claim 11 , wherein:

the removing the second spacers results correspondingly in exposed sidewalls of the first spacers and of the first ESL portions; and

the forming second ESL portions includes:

relative to a reference direction parallel to a plane of the semiconductor substrate, removing portions of the second ESL portions resulting corresponding in the exposed regions of the first spacers and of the first ESL portions the exposed regions of the first spacers and of the first ESL portions being perpendicular correspondingly to the sidewalls of the first spacers and of the first ESL portions.

17. The method of claim 9 , wherein:

relative to a reference direction parallel to a plane of the semiconductor substrate, a width of a representative one of the first spacers is substantially the same as a width of a representative one of the first ESL portions.

18. A method of manufacturing fins for a semiconductor device, the method comprising:

forming a first layer on a semiconductor substrate, the first layer having first spacers, second spacers and first etch stop layer (ESL) portions which are interspersed such that each of the first spacers and is abutted by corresponding ones of the second spacers, and each of the first ESL portions is abutted by corresponding ones of the second spacers;

forming second ESL portions correspondingly on the first spacers and the first ESL portions;

removing the second spacers;

removing exposed regions of the first spacers and the first ESL portions and corresponding underlying portions of the semiconductor substrate;

removing the second ESL portions resulting in corresponding first capped semiconductor fins and second capped semiconductor fins, the first and second capped semiconductor fins being organized into at least first and second sets;

each member of the first set having a first cap with a first etch sensitivity; and

each member of the second set having a second cap with a second etch sensitivity, the second etch sensitivity being different than the first etch sensitivity; and

eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.

19. The method of claim 18 , wherein the forming a first layer includes:

forming first mandrel features spaced apart on the semiconductor substrate resulting in first exposed regions of the semiconductor substrate;

forming fourth spacers on portions of the first exposed regions of the semiconductor substrate and correspondingly abutting sidewalls of the first mandrel features resulting in second exposed regions of the semiconductor substrate;

removing the first mandrel features resulting in third exposed regions of the semiconductor substrate;

forming the first spacers on portions of the third exposed regions of the semiconductor substrate and correspondingly abutting sidewalls of the fourth spacers;

removing the fourth spacers resulting in fourth exposed areas of the semiconductor substrate;

forming the second spacers on portions of the third exposed regions of the semiconductor substrate and correspondingly abutting sidewalls of the second spacers resulting in fifth exposed regions of the semiconductor substrate; and

forming the first ESL portions on the fifth exposed areas of the semiconductor substrate and correspondingly abutting sidewalls of the second spacers resulting in a second layer.

20. The method of claim 19 , wherein:

relative to a reference direction parallel to a plane of the semiconductor substrate:

a width of a representative one of the second exposed regions of the semiconductor substrate is smaller than a width of a representative one of the first exposed regions of the semiconductor substrate;

the width of the representative one of the second exposed regions of the semiconductor substrate is about the same as a width of a representative one of the first mandrel features; and

a width of a representative one of the first spacers is less than a width of a representative one of the fourth spacers.