Multi-chip high memory bandwidth configuration
A packaged device that carries multiple component devices uses a back-mounted structure to reduce the area of the substrates in the package. The package includes a first organic laminate substrate and a second organic laminate substrate. The first organic laminate substrate is the base substrate of the packaged device. The second organic laminate substrate has higher wiring density than the first organic laminate substrate. The second organic laminate substrate is joined to a top surface (or module mounting side) of the first organic laminate substrate. A first component device is mounted on a top surface of the second organic laminate substrate. A second component device is mounted on a bottom surface of the second organic laminate substrate. The second component device recesses into a cavity at the top surface of the first organic laminate substrate.
1 . A packaged device comprising:
a first organic laminate substrate;
a second organic laminate substrate that is joined onto a top surface of the first organic laminate substrate, wherein the second organic laminate substrate has a higher wiring density than the first organic laminate substrate;
a first component device mounted on a top surface of the second organic laminate substrate, the first component device including a fan out wafer level package (FOWLP) and multiple integrated circuits (ICs) that are mounted onto the FOWLP; and
a second component device mounted on a bottom surface of the second organic laminate substrate and recesses into a first cavity at the top surface of the first organic laminate substrate,
wherein the second component device has a lower power density than the first component device and is surrounded by the first organic laminate substrate at sidewalls and a bottom of the second component device.
2 . The packaged device of claim 1 , wherein the first organic laminate substrate is a laminate comprising a set of standard build-up layers and the second organic laminate substrate is a high-density interconnect (HDI) laminate.
3 . The packaged device of claim 1 , wherein the second component device is a chip stack comprising multiple integrated circuits (ICs); the first component device has a first thickness and the second component device has a second thickness; and the second thickness is thinner than the first thickness.
4 . The packaged device of claim 1 , wherein the first organic laminate substrate comprises a heat conducting path that is configured to dissipate heat from the first cavity emitted by the second component device, and wherein the first cavity in the first organic laminate substrate has a depth that is shallower than a thickness of the first organic laminate substrate.
5 . The packaged device of claim 1 , wherein the first component device is mounted on the top surface of the second organic laminate substrate at the FOWLP, the FOWLP further includes a fine pitch redistribution layer (RDL).
6 . The packaged device of claim 1 , wherein the second component device provides memory storage for the first component device.
7 . The packaged device of claim 6 , wherein the second component device is a high bandwidth memory (HBM) and the first component device is a central processing unit (CPU) or graphical processing unit (GPU).
8 . The packaged device of claim 1 , further comprising a conductive pillar directly contacting both a bottom surface of the second organic laminate substrate and a bottom surface of the first cavity, the conductive pillar being configured to supply power to the second organic laminate substrate from the first organic laminate substrate.
9 . The packaged device of claim 1 , wherein the second component device is mounted at a position of the second organic laminate substrate that overlaps the first component device.
10 . The packaged device of claim 1 , further comprising a third component device mounted at the bottom surface of the second organic laminate substrate and recesses into the first cavity at the top surface of the first organic laminate substrate, and a conductive pillar between the second component device and the third component device, the conductive pillar contacting the second organic laminate substrate and the first cavity.
11 . The packaged device of claim 10 , wherein the third component device provides memory storage for a fourth component device that is mounted on the second organic laminate substrate.
12 . The packaged device of claim 1 , wherein the second organic laminate substrate is soldered onto the first organic laminate substrate using control collapse of chip connection (C4) and ball grid array (BGA).
13 . A method for fabricating a packaging device, the method comprising:
providing a first organic laminate substrate and a second organic laminate substrate joined onto a top surface of the first organic laminate substrate, wherein the second organic laminate substrate has a higher wiring density than the first organic laminate substrate;
bonding a first component device on a top surface of the second organic laminate substrate, the first component device including a fan out wafer level package (FOWLP) and multiple integrated circuits (ICs) that are mounted onto the FOWLP;
bonding a second component device on a bottom surface of the second organic laminate substrate;
forming a cavity at the top surface of the first organic laminate substrate; and
mounting the second organic laminate substrate onto the first organic laminate substrate, wherein the second component device is recessed into the cavity of the first organic laminate substrate and has a lower power density than the first component device and is surrounded by the first organic laminate substrate at sidewalls and a bottom of the second component device.
14 . A device comprising:
an organic laminate substrate;
a high density interconnect (HDI) on a top surface of the organic laminate substrate;
a first component device on a top surface of the HDI;
a second component device on a bottom surface of the HDI, the second component device recesses into a first cavity in the organic laminate substrate; and
a conductive pillar having a first and a second end, the first end being in direct contact with the bottom surface of the HDI and the second end being in direct contact with a bottom surface of the first cavity.
15 . The device of claim 14 , wherein the first component device has a first thickness and the second component device has a second thickness that is thinner than the first thickness.
16 . The device of claim 14 , further comprising a third component device mounted at the bottom surface of the HDI, the third component device recesses into a second cavity of the organic laminate substrate.
17 . The device of claim 16 , wherein the first and the second cavity in the organic laminate substrate have a substantially same depth that is shallower than a thickness of the organic laminate substrate, the first and the second cavity do not extend to the bottom of the organic laminate substrate.
18 . The device of claim 14 , wherein the first component device includes a fan out wafer level package (FOWLP) and multiple integrated circuits (ICs), the multiple ICs are mounted onto the FOWLP, and the FOWLP includes a fine pitch redistribution layer (RDL).
19 . The device of claim 14 , wherein the conductive pillar provides power to the HDI from the organic laminate substrate.
20 . The device of claim 14 , further comprising a third component device mounted at the bottom surface of the HDI, the third component device recesses into the first cavity of the organic laminate substrate, and further comprising a conductive pillar vertically in direct contact with both the bottom surface of the HDI and a bottom surface of the first cavity, the second component device being at a first side of the conductive pillar and the third component device being at a second side, opposite the first side, of the conductive pillar.