Packaging architecture for modular die interoperability

1 . A microelectronic assembly comprising:

a first plurality of integrated circuit (IC) dies arranged in an array of rows and columns in a first layer; and

a second plurality of IC dies in a second layer not coplanar with the first layer, wherein:

a first IC die in the first plurality is differently sized than surrounding IC dies in the first plurality, and

a second IC die in the second plurality coupled to the first IC die comprises a repeater circuitry in an electrical pathway coupling the first IC die with an adjacent IC die in the first plurality, wherein the repeater circuitry comprises an amplifier, and the second IC die is part of an array of bridge dies having smaller sizes than the surrounding IC dies in the first plurality.

2 . The microelectronic assembly of claim 1 , wherein:

the first IC die is larger than the surrounding IC dies, and

the second IC die is at least one of longer and wider than adjacent IC dies in the second plurality.

3 . The microelectronic assembly of claim 1 , wherein:

the second plurality of IC dies is embedded in a dielectric in the second layer, and

through-dielectric vias (TDVs) in the second layer provide electrical coupling between the first layer and a third layer.

4 . The microelectronic assembly of claim 1 , further comprising a redistribution layer (RDL) between the second layer and a package substrate.

5 . The microelectronic assembly of claim 1 , further comprising a third IC die in the first layer coupled mechanically to the second IC die, wherein the third IC die does not comprise any functional electrical circuits.

6 . The microelectronic assembly of claim 1 , wherein:

a third IC die in the first plurality of IC dies has an incompatible communication interface with adjacent IC dies in the first plurality, and

a fourth IC die in the second plurality of IC dies comprises a circuit for protocol translation that enables the third IC die to communicate with the adjacent IC dies.

7 . The microelectronic assembly of claim 1 , further comprising other IC dies in the first layer that are not part of the first plurality.

8 . An IC package comprising:

a first IC die in a first layer;

a second IC die in a second layer between the first layer and a third layer; and

a package substrate in the third layer, wherein:

the first IC die is part of an array of uniformly sized IC dies in the first layer,

the first IC die is differently sized than the uniformly sized IC dies,

the second IC die is part of another array of bridge dies having smaller sizes than the array of uniformly sized IC dies; and

the second IC die comprises a repeater circuitry in an electrical pathway coupling the first IC die with an adjacent IC die in the array of uniformly sized IC dies, the repeater circuitry comprising an amplifier.

9 . The IC package of claim 8 , wherein a RDL between the second layer and the third layer accommodates electrical routing for the differently sized first IC die.

10 . The IC package of claim 8 , wherein:

the first IC die has a first interface for communication with an adjacent IC die,

the adjacent IC die has a second interface for communication with the first IC die,

the first interface and the second interface are incompatible, such that the first IC die cannot communicate with the adjacent IC die, and

the second IC die comprises a circuit for protocol translation between the first interface and the second interface, such that the first IC die is enabled to communicate with the adjacent IC die through the circuit.

11 . The IC package of claim 8 , wherein the second layer comprises a dielectric with TDVs surrounding the second IC die.

12 . The IC package of claim 11 , wherein the dielectric comprises inorganic material.

13 . The IC package of claim 8 , wherein the package substrate comprises one of a silicon interposer and an organic substrate.

14 . A server architecture comprising:

an array of core complexes in individual IC dies in a first layer, electrically coupled along edges of the individual IC dies by bridge dies in a second layer not coplanar with the first layer, wherein:

the array forms a modular tiled compute architecture,

at least one IC die has a different footprint than other IC dies in the first layer and a different routing from the other IC dies in the first layer, wherein an RDL between the second layer and a package substrate accommodates the different routing, and

at least one bridge die electrically coupled to the at least one IC die comprises a repeater circuitry in an electrical pathway coupling the at least one IC die with an adjacent IC die in the first layer, the repeater circuitry configured to amplify a signal in the electrical pathway.

15 . The server architecture of claim 14 , wherein:

the at least one bridge die comprises the repeater circuitry, and

the at least one bridge die is larger than adjacent bridge dies in the second layer.

16 . The server architecture of claim 14 , wherein:

one of the core complexes is in another IC die that has an incompatible communication interface with other adjacent IC dies, and

another one of the bridge dies electrically coupled to the another IC die comprises circuitry for protocol translation that enables the another IC die to communicate with the other adjacent IC dies.

17 . The IC package of claim 8 , wherein the first IC die is larger than the uniformly sized IC dies.

18 . The server architecture of claim 14 , wherein the at least one IC die has a larger footprint than the other IC dies in the first layer.

19 . The server architecture of claim 14 , wherein the at least one bridge die in the second layer has a smaller footprint than the individual IC dies in the first layer.

20 . The IC package of claim 8 , wherein the first IC die has different routing from the uniformly sized IC dies.