Low temperature bonded structures
Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
1. A microelectronic assembly, comprising:
a first substrate having a first bonding surface;
a second substrate having a second bonding surface, the second bonding surface bonded to the first bonding surface; and
a bonded conductive interconnect disposed at the first bonding surface and the second bonding surface, the bonded conductive interconnect comprising at least a first conductive material, a second conductive material, and a conductive mass comprising a combination of materials including a third conductive material, disposed between the first conductive material and the second conductive material, wherein a concentration of the third conductive material is non-linear within the conductive mass.
2. The microelectronic assembly of claim 1 , further comprising a barrier layer disposed between the first conductive material and the conductive mass, between the second conductive material and the conductive mass, or between the first conductive material and the conductive mass and between the second conductive material and the conductive mass, the barrier layer comprising a different conductive material than the first, second, or third conductive materials.
3. The microelectronic assembly of claim 1 , wherein the conductive mass further comprises a fourth conductive material, and wherein a concentration of the fourth conductive material is non-linear within the conductive mass.
4. The microelectronic assembly of claim 1 , wherein the third conductive material is different than the first or second conductive materials.
5. The microelectronic assembly of claim 1 , wherein the third conductive material comprises a discontinuous layer of material.
6. The microelectronic assembly of claim 1 , wherein the first conductive material is a different material from the material of the second conductive material.
7. The microelectronic assembly of claim 1 , wherein a melting point of the conductive mass is higher than respective melting points of the first and second conductive materials.
8. A microelectronic assembly, comprising:
a first substrate having a first surface with a first conductive material embedded therein;
a second substrate having a second surface with a second conductive material embedded therein, the first surface bonded to the second surface; and
an electrically conductive mass coupling the first conductive material to the second conductive material, wherein the conductive mass includes the first conductive material, the second conductive material, and a third conductive material, and wherein a concentration of the first material, the second material, and the third material is non-linear within the conductive mass.
9. The microelectronic assembly of claim 8 , wherein a concentration of the first material in the electrically conductive mass is greater than a concentration of the second material.
10. The microelectronic assembly of claim 8 , further comprising a conductive barrier layer disposed between the first substrate and the first conductive material and/or between the second substrate and the second conductive material.
11. The microelectronic assembly of claim 8 , wherein at least one of the first material, the second material, and the third material is a non-metal material.
12. The microelectronic assembly of claim 8 , wherein a concentration of the first conductive material varies from a relatively higher amount at a location disposed toward the first substrate to a relatively lower amount toward the second substrate, and wherein a concentration of the second conductive material varies in concentration from a relatively higher amount at a location disposed toward the second substrate to a relatively lower amount toward the first substrate.
13. The microelectronic assembly of claim 8 , further comprising a first dielectric region located at the first surface and a second dielectric region located at the second surface, the second dielectric region being in contact with and directly bonded to the first dielectric region without adhesive.