IP Library Granted Patent US 12,653,039
Granted Patent B2
US 12,653,039 · App. 18/186,202 · Granted Jun 9, 2026

Semiconductor device and method of forming the same

Inventors: Yung-Chi Lin (New Taipei City, TW); Ming-Tsu Chung (Hsinchu, TW); Yan-Zuo Tsai (Hsinchu City, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10W70/417H10W46/00H10W70/05H10W90/00H10W46/301
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Quick Facts
Patent No.
US 12,653,039
App. No.
18/186,202
Granted
Jun 9, 2026
Kind
B2
Abstract

A semiconductor device includes a first die. The first die includes a first dielectric bonding layer thereon and a plurality of first dielectric bonding patterns in the first dielectric bonding layer. A composition of the first dielectric bonding patterns is different from a composition of the first dielectric bonding layer.

Claims (32)

1 . A semiconductor device, comprising:

a first die having an interconnect structure and a first dielectric bonding layer covering a top surface of the interconnect structure; and

a plurality of first dielectric bonding patterns in the first dielectric bonding layer, wherein a composition of the first dielectric bonding patterns is different from a composition of the first dielectric bonding layer, wherein first surfaces of the first dielectric bonding patterns are substantially coplanar with a first surface of the first dielectric bonding layer, and second surfaces opposite to the first surfaces of the first dielectric bonding patterns are substantially coplanar with a second surface opposite to the first surface of the first dielectric bonding layer.

2 . The semiconductor device of claim 1 , wherein the first dielectric bonding layer has a bonding region and a non-bonding region, and a density of the first dielectric bonding patterns in the bonding region is not smaller than a density of the first dielectric bonding patterns in the non-bonding region.

3 . The semiconductor device of claim 1 , wherein the first dielectric bonding layer and the first dielectric bonding patterns respectively include SiO x N y C z , x=0 to 2, y=0 to 1.33,z=0 to 1, and x, y and z are not all equal to zero.

4 . The semiconductor device of claim 3 , wherein the first dielectric bonding layer and the first dielectric bonding patterns respectively include SiO 2 , SiON, SiOC, SiN, SiCN, SiC, SiON or a combination thereof.

5 . The semiconductor device of claim 1 , wherein the first dielectric bonding layer has a plurality of non-bonding regions and a bonding region disposed between the non-bonding regions, and a density of the first dielectric bonding patterns in the bonding region is not smaller than a density of the first dielectric bonding patterns in the non-bonding regions.

6 . The semiconductor device of claim 2 , wherein the bonding region has a first surface facing the interconnect structure and a second surface opposite to the first surface of the bonding region, the non-bonding region has a first surface facing the interconnect structure and a second surface opposite to the first surface of the non-bonding region, and the first surface of the bonding region is substantially coplanar to with the first surface of the non-bonding region.

7 . The semiconductor device of claim 6 , wherein the second surface of the bonding region is substantially coplanar with the second surface of the non-bonding region.

8 . The semiconductor device of claim 2 , wherein the interconnect structure and the first dielectric bonding layer are stacked along a first direction, and the bonding region and the non-bonding region are not overlapped along the first direction.

9 . A semiconductor device, comprising:

a first package component having an interconnect structure, a first dielectric bonding layer covering a top surface of the interconnect structure and a plurality of first dielectric bonding patterns in the first dielectric bonding layer, wherein an interface exists between the first dielectric bonding layer and the first dielectric bonding pattern; and

a second package component having a second dielectric bonding layer thereon and a plurality of second dielectric bonding patterns in the second dielectric bonding layer, wherein the first package component and the second package component are bonded through the first dielectric bonding layer and the second dielectric bonding layer and through the first dielectric bonding patterns and the second dielectric bonding layer, wherein each of the second dielectric bonding patterns is bonded to at least one of the first dielectric bonding layer and the first dielectric bonding pattern.

10 . The semiconductor device of claim 9 , wherein first surfaces of the first dielectric bonding patterns are substantially coplanar with a first surface of the first dielectric bonding layer, and first surfaces of the second dielectric bonding patterns are substantially coplanar with a first surface of the second dielectric bonding layer.

11 . The semiconductor device of claim 9 , wherein the first dielectric bonding layer and the first dielectric bonding patterns are in direct contact with the second dielectric bonding layer.

12 . The semiconductor device of claim 9 , wherein a material of the first dielectric bonding patterns is different from a material of the first dielectric bonding layer.

13 . The semiconductor device of claim 9 , wherein the first dielectric bonding layer and the first dielectric bonding patterns respectively include SiO x N y C z , x=0 to 2, y=0 to 1.33, z=0 to 1, and x, y and z are not all equal to zero.

14 . The semiconductor device of claim 9 , wherein the first dielectric bonding layer and the first dielectric bonding patterns respectively include SiO 2 , SiON, SiOC, SIN, SiCN, SiC, SiON or a combination thereof.

15 . The semiconductor device of claim 9 , wherein the first dielectric bonding layer has a first surface facing the second package, one of the first dielectric bonding patterns has a first surface facing the second package, and the first surface of the first dielectric bonding layer is substantially coplanar with the first surface of the one of the first dielectric bonding patterns.

16 . A method of forming a semiconductor device, comprising:

providing a first package component having a first dielectric bonding layer thereon;

forming a plurality of first dielectric bonding patterns in the first dielectric bonding layer, comprising:

forming a plurality of openings in the first dielectric bonding layer;

forming the first dielectric bonding patterns respectively in the openings; and

performing a chemical mechanical polishing process, so that surfaces of the first dielectric bonding patterns are substantially coplanar with a surface of the first dielectric bonding layer,

wherein opposite sidewalls of one of the first dielectric bonding patterns are physically connected to the first dielectric bonding layer;

providing a second package component having a second dielectric bonding layer thereon; and

bonding the first package component and the second package component through the first dielectric bonding layer and the second dielectric bonding layer.

17 . The method of claim 16 , further comprising forming a plurality of second dielectric bonding patterns in the second dielectric bonding layer, wherein the first package component and the second package component are further bonded through bonding the first dielectric bonding patterns and the second dielectric bonding patterns.

18 . The method of claim 16 , wherein the first package component has a bonding region bonded to the second package component and a non-bonding region aside the bonding region, and a density of the first dielectric bonding patterns in the bonding region is not smaller than a density of the first dielectric bonding patterns in the non-bonding region.

19 . The semiconductor device of claim 17 , wherein one of the second dielectric bonding patterns is bonded to at least one of the first dielectric bonding layer and the first dielectric bonding pattern.

20 . The semiconductor device of claim 17 , wherein surfaces of the second dielectric bonding patterns are substantially coplanar with a surface of the second dielectric bonding layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2023
From: LIN, YUNG-CHI; CHUNG, MING-TSU; TSAI, YAN-ZUO
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 063052/0740 →
Continuity (1)
Related Publication 20240321694A1 · Sep 26, 2024
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