Semiconductor device with multiple independent gates
Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.
1. A gate-controlled semiconductor device comprising:
a first plurality of cells of said semiconductor device configured to be controlled by a primary gate;
a second plurality of cells of said semiconductor device configured to be controlled by an auxiliary gate,
wherein said primary gate is electrically isolated from said auxiliary gate,
wherein said primary gate and said auxiliary gate are electrically isolated from sources and drains of said semiconductor device, and
wherein sources and drains of said semiconductor device are electrically coupled in parallel.
2. The semiconductor device of claim 1 wherein said first and second pluralities of cells are substantially identical in structure.
3. The semiconductor device of claim 1 wherein each cell of said first plurality of cells comprises a trench comprising a gate electrode.
4. The semiconductor device of claim 3 wherein said trench comprises a shield electrode, electrically isolated from said gate electrode.
5. The semiconductor device of claim 4 wherein said shield electrode is coupled to a source potential.
6. The semiconductor device of claim 1 wherein an effective resistance of said second plurality of cells is characterized as in the range of 50-200 times an effective resistance of said first plurality of cells.
7. The semiconductor device of claim 1 wherein said second plurality of cells are configured to have a threshold voltage that is different from a threshold voltage of said first plurality of cells.
8. The semiconductor device of claim 1 further comprising a Zener diode coupled between said auxiliary gate and a common drain of said semiconductor device.
9. The semiconductor device of claim 8 wherein a nominal voltage of said Zener diode is in a range of 10-15% below a rated voltage of said first plurality of cells.
10. The semiconductor device of claim 1 further comprising a clamping circuit coupled between said auxiliary gate and a common drain of said semiconductor device, wherein a nominal clamping voltage of said clamping circuit is below an avalanche breakdown voltage of said first plurality of cells.
11. A gate-controlled semiconductor device comprising:
a source terminal;
a drain terminal;
a primary gate terminal configured to control current from said drain terminal to said source terminal in a first fraction of channel area of said semiconductor device; and
an auxiliary gate terminal configured to control current from said drain terminal to said source terminal in a second fraction of channel area of said semiconductor device,
wherein said primary gate terminal, said auxiliary gate terminal, said source terminal and said drain terminal are electrically isolated from one another.
12. The semiconductor device of claim 11 further comprising a channel region comprising silicon.
13. The semiconductor device of claim 11 wherein said auxiliary gate terminal is electrically coupled to said drain terminal on a die of said semiconductor device.
14. The semiconductor device of claim 11 wherein said auxiliary gate terminal is electrically coupled to said source terminal via an explicit resistance on a die of said semiconductor device.
15. A gate-controlled semiconductor device comprising:
a plurality of primary cells, comprising:
a primary source, a primary drain, and primary channel regions;
a primary gate electrode coupled to a primary gate terminal of said semiconductor device;
a plurality of auxiliary cells, comprising:
an auxiliary source, an auxiliary drain, and auxiliary channel regions;
an auxiliary gate electrode coupled to an auxiliary gate terminal of said semiconductor device,
wherein said primary source and said primary drain are coupled in parallel with said auxiliary source and said auxiliary drain forming a common source and a common drain, and
wherein said primary gate terminal, said auxiliary gate terminal, said common source and said common drain are electrically isolated from one another.
16. The semiconductor device of claim 15 wherein an effective resistance of all of said auxiliary channel regions is in a range of 90-100 times an effective resistance of all of said primary channel regions.
17. The semiconductor device of claim 15 wherein said plurality of auxiliary cells are evenly and regularly distributed among said plurality of primary cells.
18. The semiconductor device of claim 15 further comprising a Zener diode coupled between said auxiliary gate terminal and said common drain on a same die of said semiconductor device.
19. The semiconductor device of claim 15 further comprising an explicit resistance coupled between said auxiliary gate terminal and said common source on a same die of said semiconductor device.
20. The semiconductor device of claim 15 wherein said auxiliary gate terminal is coupled to an external package terminal.