Compute in memory (CIM) memory array

1. A memory device for compute-in-memory (CIM), comprising:

a memory array including a plurality of memory cells arranged in an array of rows and columns, the memory cells including a first group of memory cells and a second group of memory cells;

a plurality of word lines, each row of the array having a corresponding word line, each memory cell of a row of the array coupled to the corresponding word line;

a plurality of bit lines, each column of the array having a corresponding bit line, each memory cell of a column of the array coupled to the corresponding bit line;

a control circuit configured to select the first group of memory cells and/or the second group of memory cells in response to a group enable signal;

an input terminal configured to receive a CIM input signal; and

a multiply circuit configured to receive weight signals stored in the selected group of memory cells and multiply the weight signals by the CIM input signal to generate a plurality of partial products.

2. The memory device of claim 1 , further comprising:

a first sense amplifier coupled to the bit lines of the first group of memory cells; and

a second sense amplifier coupled to the bit lines of the second group of memory cells.

3. The memory device of claim 2 , further comprising a multiplexer (MUX) connected to the first sense amplifier and the second sense amplifier.

4. The memory device of claim 3 , wherein the multiply circuit is connected to an output terminal of the MUX.

5. The memory device of claim 1 , wherein each of the memory cells includes one transistor and one capacitor for forming a one-transistor one capacitor (1T-1C) memory cell.

6. The memory device of claim 5 , wherein the transistor of the 1T-1C memory cell includes a gate terminal connected to its respective word line.

7. The memory device of claim 5 , wherein the transistor of the 1T-1C memory cell includes:

a first source/drain (S/D) terminal connected to its respective bit line; and

a second source/drain (S/D) terminal connected to a first terminal of the capacitor of the 1T-1C memory cell.

8. The memory device of claim 5 , wherein the memory array includes a power input terminal configured to receive a VDD voltage, and wherein the capacitor of the 1T-1C memory cell includes a second terminal connected to receive a half VDD voltage.

9. The memory device of claim 1 , wherein the memory cells further include a third group of memory cells and a fourth group of memory cells.

10. The memory device of claim 9 , wherein the control circuit is configured to select the first and third groups of memory cells or the second and fourth groups of memory cells in response to a one-bit group enable signal.

11. The memory device of claim 9 , wherein the control circuit is configured to select the first group, the second group, the third group or the fourth group of memory cells in response to a two-bit group enable signal.

12. The memory device of claim 1 , wherein the control circuit includes:

a first control circuit connected to the bit lines of a first column of the memory array; and

a second control circuit connected to the bit lines of a second column of the memory array.

13. A compute in memory (CIM) device, comprising:

a plurality of memory cells configured to store weight signals, the memory cells arranged in an array of rows and columns including a first group of memory cells and a second group of memory cells;

a plurality of word lines, each row of the array having a corresponding word line, each memory cell coupled to the corresponding word line;

a plurality of bit lines, each column of the array having a corresponding bit line, each memory cell coupled to the corresponding bit line;

a sense amplifier coupled to the bit lines and configured to amplify signals of the bit lines for reading operations;

a control circuit connected to the bit lines and configured to select the first group of memory cells or the second group of memory cells in response to a group enable signal;

an input terminal configured to receive a CIM input signal; and

a multiply circuit configured to multiply the weight signals by the CIM input signal to generate a plurality of partial products.

14. The CIM device of claim 13 , further comprising a multiplexer (MUX) connected to the sense amplifier.

15. The CIM device of claim 13 , wherein each of the memory cells includes one transistor and one capacitor for forming a one-transistor one capacitor (1T-1C) memory cell.

16. The CIM device of claim 13 , wherein the memory cells further include a third group of memory cells and a fourth group of memory cells.

17. The CIM device of claim 13 , further comprising a one IO adder tree circuit configured to add the plurality of partial products.

18. A method, comprising:

providing a memory array having a plurality of memory cells arranged in an array of rows and columns, the memory cells including a first group of memory cells and a second group of memory cells;

providing a plurality of word lines, each row of the array having a corresponding word line, each memory cell of a row of the array coupled to the corresponding word line;

providing a plurality of bit lines, each column of the array having a corresponding bit line, each memory cell of a column of the array coupled to the corresponding bit line;

receiving a group enable signal;

performing a first operation on the first group of memory cells in response to the group enable signal;

performing a second operation on the second group of memory cells in response to the group enable signal;

writing compute in memory (CIM) weight signals to the memory cells;

reading the CIM weight signals from the memory cells;

receiving a CIM input signal; and

multiplying the CIM input signal by the CIM weight signals by a multiply circuit.

19. The method of claim 18 , wherein the first operation is a read operation and the second operation is a write operation.

20. The method of claim 18 , wherein the first operation and the second operation are performed simultaneously.