Compute in memory (CIM) memory array for storing weights
A memory device for CIM has a memory array including a plurality of memory cells arranged in an array of rows and columns. The memory cells have a first group of memory cells and a second group of memory cells. Each row of the array has a corresponding word line, with each memory cell of a row of the array coupled to the corresponding word line. Each column of the array has a corresponding bit line, with each memory cell of a column of the array coupled to the corresponding bit line. A control circuit is configured to select the first group of memory cells or the second group of memory cells in response to a group enable signal.
1 . A memory device for compute-in-memory (CIM), comprising:
a memory array including a plurality of memory cells arranged in an array of rows and columns, the memory cells including a first group of memory cells and a second group of memory cells;
a plurality of word lines, each row of the array having a corresponding word line, each memory cell of a row of the array coupled to the corresponding word line;
a plurality of bit lines, each column of the array having a corresponding bit line, each memory cell of a column of the array coupled to the corresponding bit line the plurality of bit lines including even numbered bit lines and odd numbered bit lines, wherein the first group of memory cells are connected to the even numbered bit lines and the second group of memory cells are connected to the odd numbered bit lines; and
a control circuit configured to select the first group of memory cells or the second group of memory cells in response to a group enable signal;
wherein, responsive to the control circuit selecting the first group of memory cells, a word line associated with a selected group of memory cells is activated and an associated bit line is driven to a desired value to selectively write CIM weight values to the first group of memory cells and simultaneously perform a read or write operation on the second group of memory cells.
2 . The memory device of claim 1 , further comprising:
a first sense amplifier coupled to the bit lines of the first group of memory cells; and
a second sense amplifier coupled to the bit lines of the second group of memory cells.
3 . The memory device of claim 2 , further comprising a multiplexer (MUX) connected to the first sense amplifier and the second sense amplifier.
4 . The memory device of claim 2 , wherein the control circuit is further configured to control the first sense amplifier and the second sense amplifier.
5 . The memory device of claim 1 , wherein each of the memory cells includes one transistor and one capacitor for forming a one-transistor one capacitor (1T-1C) memory cell.
6 . The memory device of claim 5 , wherein a transistor of the 1T-1C memory cell includes a gate terminal connected to its respective word line.
7 . The memory device of claim 5 , wherein the transistor of the 1T-1C memory cell includes:
a first source/drain (S/D) terminal connected to its respective bit line; and
a second source/drain (S/D) terminal connected to a first terminal of a capacitor of the 1T-1C memory cell.
8 . The memory device of claim 5 , wherein the memory array includes a power input terminal configured to receive a VDD voltage, and wherein a capacitor of the 1T-1C memory cell includes a second terminal connected to receive a half VDD voltage.
9 . A memory device for compute-in-memory (CIM), comprising:
a memory array including a plurality of memory cells arranged in an array of rows and columns, the memory cells including a first group of memory cells and a second group of memory cells;
a plurality of word lines, each row of the array having a corresponding word line, each memory cell of a row of the array coupled to the corresponding word line;
a plurality of bit lines, each column of the array having a corresponding bit line, each memory cell of a column of the array coupled to the corresponding bit line the plurality of bit lines including even numbered bit lines forming a first group of memory cells and odd numbered bit lines forming a second group of memory cells; and
a multiply circuit configured to receive weight signals stored in a selected group of memory cells and multiply the weight signals by a CIM input signal to generate a plurality of partial products
wherein, responsive to a select signal selecting the selected group of memory cells, the plurality of bit lines and the plurality of word lines perform a read or write operation on the first group of memory cells and a simultaneous read or write operation on the second group of memory cells in the memory array.
10 . The memory device of claim 9 , further comprising:
a sensing amplifier coupled to the bit lines and configured to amplify signals of the bit lines for reading operations; and
a multiplexer (MUX) connected to the sensing amplifier.
11 . The memory device of claim 10 , further comprising:
a control circuit configured to control the sensing amplifier.
12 . The memory device of claim 9 , further comprising:
an adder circuit configured to add the plurality of partial products to produce a CIM output.
13 . The memory device of claim 9 , wherein the multiply circuit is configured to perform a bit-serial multiplication of an input signal and the weight signals from a most significant bit to a least significant bit.
14 . The memory device of claim 9 , wherein each of the memory cells includes one transistor and one capacitor for forming a one-transistor one capacitor (1T-1C) memory cell.
15 . The memory device of claim 14 , wherein the transistor of the 1T-1C memory cell includes a gate terminal connected to its respective word line.
16 . The memory device of claim 14 , wherein the transistor of the 1T-1C memory cell includes:
a first source/drain (S/D) terminal connected to its respective bit line; and
a second source/drain (S/D) terminal connected to a first terminal of a capacitor of the 1T-1C memory cell.
17 . A method, comprising:
providing a memory array having a plurality of memory cells arranged in an array of rows and columns, the memory cells including a first group of memory cells and a second group of memory cells;
providing a plurality of word lines, each row of the array having a corresponding word line, each memory cell of a row of the array coupled to the corresponding word line;
providing a plurality of bit lines, each column of the array having a corresponding bit line, each memory cell of a column of the array coupled to the corresponding bit line;
performing a read operation on the first group of memory cells in response to a group enable signal; and
performing, simultaneously to performing the read operation on the first group, a write operation on the second group of memory cells in response to the group enable signal.
18 . The method of claim 17 , further comprising:
writing compute in memory (CIM) weight signals to the memory cells;
receiving a CIM input signal; and
multiplying the CIM input signal by the CIM weight signals by a multiply circuit.
19 . The method of claim 17 , further comprising:
receiving, by a control circuit, the group enable signal; and
responsive to receiving the group enable signal, selecting, by the control circuit, the first group of memory cells.
20 . The method of claim 17 , further comprising:
performing, simultaneously to performing the read operation on the first group, a read operation on the second group of memory cells in response to the group enable signal.