IP Library › Granted Patent US 12,642,120
Granted Patent B2
US 12,642,120 · App. 17/561,730 · Granted May 26, 2026

Ultra low loss and high-density routing between cores

Inventors: Arghya Sain (Chandler, AZ); Andrew P. Collins (Chandler, AZ); Sivaseetharaman Pandi (Chandler, AZ); Jianyong Xie (Chandler, AZ); Telesphor Kamgaing (Chandler, AZ)
Assignee: Intel Corporation
H10W70/692H10W70/095H10W70/635H10W70/685H10W90/724
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Quick Facts
Patent No.
US 12,642,120
App. No.
17/561,730
Granted
May 26, 2026
Kind
B2
Abstract

Embodiments disclosed herein include a package core. In an embodiment, the package core includes a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises glass. In an embodiment, a third layer is over the second layer, where the third layer comprises glass. In an embodiment, a first trace is between the first layer and the second layer. In an embodiment, a second trace is between the second layer and the third layer.

Claims (83)

1 . A package core, comprising:

a first layer, wherein the first layer comprises glass;

a second layer over the first layer, wherein the second layer comprises glass;

a third layer over the second layer, wherein the third layer comprises glass, wherein a first adhesive couples the first layer to the second layer, and a second adhesive couples the second layer to the third layer;

a first trace between an uppermost surface of the first layer and a bottommost surface of the second layer; and

a second trace between an uppermost surface of the second layer and a bottommost surface of the third layer.

2 . The package core of claim 1 , wherein the first trace has a thickness that is substantially equal to a thickness of the first adhesive, and wherein the second trace has a thickness that is substantially equal to a thickness of the second adhesive.

3 . The package core of claim 1 , further comprising:

first vias that couple the first trace to a top surface and a bottom surface of the core; and

second vias that couple the second trace to a top surface and a bottom surface of the core.

4 . The package core of claim 1 , further comprising:

a first via that couples a first end of the second trace to a top surface of the core; and

a second via that couples a second end of the second trace to the top surface of the core.

5 . The package core of claim 4 , further comprising:

a third via that couples a first end of the first trace to the top surface of the core; and

a fourth via that couples a second end of the first trace to the top surface of the core.

6 . The package core of claim 4 , further comprising:

a third via that couples a first end of the first trace to the top surface of the core; and

a fourth via that couples a second end of the first trace to a bottom surface of the core.

7 . The package core of claim 1 , further comprising:

cavities into the first layer and the second layer, wherein the first trace fills the cavities.

8 . The package core of claim 1 , further comprising:

a first conductive plane over a top surface of the core; and

a second conductive plane over a bottom surface of the core.

9 . The package core of claim 8 , further comprising:

a first cavity into the top surface of the core, wherein the first cavity is filled by the first conductive plane; and

a second cavity into the bottom surface of the core, wherein the second cavity is filled by the second conductive plane.

10 . The package core of claim 1 , wherein the first trace and the second trace are part of dual stripline routing architectures.

11 . An electronic system, comprising:

a board;

a package substrate coupled to the board, wherein the package substrate comprises:

a first layer, wherein the first layer comprises glass;

a second layer over the first layer, wherein the second layer comprises glass;

a third layer over the second layer, wherein the third layer comprises glass;

a first trace between an uppermost surface of the first layer and a bottommost surface of the second layer; and

a second trace between an uppermost surface of the second layer and a bottommost surface of the third layer; and

a die coupled to the package substrate.

12 . The electronic system of claim 11 , wherein a first adhesive couples the first layer to the second layer, and a second adhesive couples the second layer to the third layer.

13 . The electronic system of claim 12 , wherein the first trace has a thickness that is substantially equal to a thickness of the first adhesive, and wherein the second trace has a thickness that is substantially equal to a thickness of the second adhesive.

14 . A package core, comprising:

a first layer, wherein the first layer comprises glass;

a second layer over the first layer, wherein the second layer comprises glass;

a third layer over the second layer, wherein the third layer comprises glass;

a first trace between an uppermost surface of the first layer and a bottommost surface of the second layer;

a second trace between an uppermost surface of the second layer and a bottommost surface of the third layer;

first vias that couple the first trace to a top surface and a bottom surface of the core; and

second vias that couple the second trace to a top surface and a bottom surface of the core.

15 . The package core of claim 14 , wherein the first trace and the second trace are part of dual stripline routing architectures.

16 . A package core, comprising:

a first layer, wherein the first layer comprises glass;

a second layer over the first layer, wherein the second layer comprises glass;

a third layer over the second layer, wherein the third layer comprises glass;

a first trace between an uppermost surface of the first layer and a bottommost surface of the second layer;

a second trace between an uppermost surface of the second layer and a bottommost surface of the third layer;

a first via that couples a first end of the second trace to a top surface of the core; and

a second via that couples a second end of the second trace to the top surface of the core.

17 . The package core of claim 16 , further comprising:

a third via that couples a first end of the first trace to the top surface of the core; and

a fourth via that couples a second end of the first trace to the top surface of the core.

18 . The package core of claim 16 , further comprising:

a third via that couples a first end of the first trace to the top surface of the core; and

a fourth via that couples a second end of the first trace to a bottom surface of the core.

19 . The package core of claim 16 , wherein the first trace and the second trace are part of dual stripline routing architectures.

20 . A package core, comprising:

a first layer, wherein the first layer comprises glass;

a second layer over the first layer, wherein the second layer comprises glass;

a third layer over the second layer, wherein the third layer comprises glass;

a first trace between an uppermost surface of the first layer and a bottommost surface of the second layer;

a second trace between an uppermost surface of the second layer and a bottommost surface of the third layer; and

cavities into the first layer and the second layer, wherein the first trace fills the cavities.

21 . The package core of claim 20 , wherein the first trace and the second trace are part of dual stripline routing architectures.

22 . A package core, comprising:

a first layer, wherein the first layer comprises glass;

a second layer over the first layer, wherein the second layer comprises glass;

a third layer over the second layer, wherein the third layer comprises glass;

a first trace between an uppermost surface of the first layer and a bottommost surface of the second layer;

a second trace between an uppermost surface of the second layer and a bottommost surface of the third layer;

a first conductive plane over a top surface of the core; and

a second conductive plane over a bottom surface of the core.

23 . The package core of claim 22 , further comprising:

a first cavity into the top surface of the core, wherein the first cavity is filled by the first conductive plane; and

a second cavity into the bottom surface of the core, wherein the second cavity is filled by the second conductive plane.

24 . The package core of claim 22 , wherein the first trace and the second trace are part of dual stripline routing architectures.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2022
From: SAIN, ARGHYA; COLLINS, ANDREW P.; PANDI, SIVASEETHARAMAN; XIE, JIANYONG; KAMGAING, TELESPHOR
To: INTEL CORPORATION
Reel/Frame 060904/0055 →
Continuity (1)
Related Publication 20230207406A1 · Jun 29, 2023
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