IP Library Granted Patent US 12,342,732
Granted Patent B2
US 12,342,732 · App. 17/564,122 · Granted Jun 24, 2025

Vertical silicon Josephson Junction device for qubit applications

Inventors: Steven J. Holmes (Ossining, NY); Devendra K. Sadana (Pleasantville, NY); Oleg Gluschenkov (Tannersville, NY); Stephen W. Bedell (Wappingers Falls, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H10N60/12G06N10/00H10N60/0912H10N60/805H10N60/85H10N69/00
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Quick Facts
Patent No.
US 12,342,732
App. No.
17/564,122
Granted
Jun 24, 2025
Kind
B2
Abstract

A vertical Josephson Junction (JJ) qubit device that is fabricated from crystalline silicon material is provided. The JJ device has a substrate of epitaxial silicon, a lower superconducting electrode that is a superconducting region of the epitaxial silicon and an upper superconducting electrode of a metallic superconductor. The JJ device also has a junction layer. A section of the junction layer between the lower and upper superconducting electrodes forms a junction of the JJ device. Resonator and/or capacitor wiring of the JJ device is also fabricated using the metallic superconductor. The superconducting region is epitaxial silicon that is doped or implanted with boron or gallium. The substrate, the junction layer, and the implanted epitaxial silicon share a contiguous crystalline structure.

Claims (33)

1. A vertical Josephson Junction device comprising:

a substrate comprising an epitaxial silicon;

a lower superconducting electrode comprising a superconducting region of the epitaxial silicon;

an upper superconducting electrode comprising a metallic superconductor; and

a junction layer, wherein:

a section of the junction layer between the lower and upper superconducting electrodes forms a junction of the vertical Josephson Junction device; and

the substrate, the lower superconducting electrode, and the junction layer have a same crystalline structure.

2. The device of claim 1 , wherein the superconducting device is a vertical Josephson Junction (JJ) qubit device.

3. The device of claim 1 , wherein the junction layer is a layer of epitaxial silicon grown over the superconducting region of the epitaxial silicon.

4. The device of claim 1 , wherein the junction layer is a layer of dielectric.

5. The device of claim 1 , wherein the superconducting region is fabricated by implanting the substrate with boron or gallium.

6. The device of claim 1 , wherein the metallic superconductor comprises a resonator and a wire.

7. The device of claim 1 , further comprising a wire in contact with the lower superconducting electrode, the wire comprising the metallic superconductor.

8. The device of claim 1 , wherein the junction layer is epitaxial silicon grown at a temperature less than 500 degree Celsius.

9. The device of claim 1 , wherein the metallic superconductor comprises aluminum.

10. A method of fabricating a superconducting device, comprising:

providing a substrate of epitaxial silicon;

doping the substrate to form a superconducting region as a lower electrode of the superconducting device;

growing epitaxial silicon over the substrate and the doped superconducting region as a junction layer of the superconducting device; and

depositing a metallic superconductor at the substrate over the junction layer as an upper electrode of the superconducting device.

11. The method of claim 10 , wherein the superconducting region is doped with boron or gallium.

12. The method of claim 10 , wherein the substrate, the superconducting region, and the junction layer share a contiguous crystalline structure.

13. The method of claim 10 , wherein the junction layer is epitaxial silicon grown at a temperature less than 500 degree Celsius.

14. The method of claim 10 , further comprising patterning regions of the epitaxial silicon substrate with resist to define contact openings to the superconducting region.

15. The method of claim 14 , further comprising performing reactive-ion etching (RIE) to remove the grown epitaxial silicon at the defined contact openings.

16. The method of claim 15 , wherein the metallic superconductor is deposited over a lift-off lithography stack and the contact openings to form a pattern for a resonator and a wire for the resonator.

17. A method of fabricating a superconducting device, comprising:

providing a substrate of epitaxial silicon;

doping the substrate to form a superconducting region as a lower electrode of the superconducting device;

depositing a dielectric layer over the substrate and the doped superconducting region as a junction layer of the superconducting device; and

depositing a metallic superconductor at the substrate over the junction layer as an upper electrode of the superconducting device.

18. The method of claim 17 , wherein the superconducting region is doped with boron or gallium.

19. The method of claim 17 , wherein the metallic superconductor comprises aluminum.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2022
From: HOLMES, STEVEN J.; SADANA, DEVENDRA K.; GLUSCHENKOV, OLEG; BEDELL, STEPHEN W.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 059617/0337 →
Continuity (1)
Related Publication 20230210018A1 · Jun 29, 2023
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