Systems and methods for qubit fabrication
A method of fabricating a superconducting-semiconducting stack includes cleaning a surface of a substrate, the substrate comprising a group IV element; depositing an insulating buffer layer onto the substrate, the insulating buffer layer comprising the group IV element; depositing a p-doped layer onto the insulating buffer layer; depositing a diffusion barrier onto the p-doped layer; and processing the superconducting-semiconducting stack through dopant activation.
1. A device, comprising:
a substrate;
a first superconducting region disposed on the substrate;
a second superconducting region disposed on the substrate and separated by the first superconducting region by a p-doped region that is heavily doped;
a Josephson junction formed by the first superconducting region, the second superconducting region, and the p-doped region; and
a gate electrode configured to electrostatically tune the Josephson junction.
2. The device of claim 1 , wherein the Josephson junction is a lateral Josephson junction.
3. The device of claim 1 , wherein the Josephson junction is a vertical Josephson junction.
4. The device of claim 1 , wherein the substrate comprises a group IV element.
5. The device of claim 1 , further comprising:
a first contact metal lead disposed on the first superconducting region; and
a second contact metal lead disposed on the second superconducting region.
6. The device of claim 5 , further comprising:
a gate dielectric layer disposed on the contact metal leads and adjacent to the gate electrode.
7. The device of claim 5 , further comprising:
a gate dielectric layer disposed adjacent to the first superconducting region and the second superconducting region.
8. The device of claim 1 , further comprising:
an insulating buffer layer disposed on the substrate.